Etendue enhancement for light emitting diode subpixels
US-2019088820-A1 · Mar 21, 2019 · US
US11784176B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11784176-B2 |
| Application number | US-202217818822-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 10, 2022 |
| Priority date | May 30, 2019 |
| Publication date | Oct 10, 2023 |
| Grant date | Oct 10, 2023 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A light emitting device includes a backplane, an array of light emitting diodes attached to a frontside of the backplane, a positive tone, imageable dielectric material layer, such as a positive photoresist layer, located on the frontside of the backplane and laterally surrounding the array of light emitting diodes, such that sidewalls of the light emitting diodes contacting the positive tone, imageable dielectric material layer have a respective reentrant vertical cross-sectional profile, and at least one common conductive layer located over the positive tone, imageable dielectric material layer and contacting the light emitting diodes.
Opening claim text (preview).
What is claimed is: 1. A method of forming a light emitting device, comprising: attaching an array of light emitting diodes to a frontside of a backplane; applying a positive tone, imageable dielectric material layer to a frontside of the backplane; vertically recessing the positive tone, imageable dielectric material layer such that a top surface of the positive tone, imageable dielectric material layer is formed below a horizontal plane including top surfaces of the light emitting diodes, wherein sidewalls of the light emitting diodes contacting the positive tone, imageable dielectric material layer have a respective reentrant vertical cross-sectional profile; and forming a transparent conductive layer over the positive tone, imageable dielectric material layer. 2. The method of claim 1 , wherein: the positive tone, imageable dielectric material layer comprises a positive photoresist layer; and sidewalls of the light emitting diodes are reverse-tapered to provide a variable horizontal cross-sectional area that increases with a vertical distance from a frontside surface of the backplane upon attaching the array of light emitting diodes to the frontside of the backplane. 3. The method of claim 2 , wherein vertically recessing the positive photoresist layer comprises performing a blanket exposure process that uncross-links a cross-linked polymer in an upper portion of the positive photoresist layer and subsequently performing a development process. 4. The method of claim 2 , wherein vertically recessing the positive photoresist layer comprises performing a blanket partial ashing process that removes an upper portion of the positive photoresist layer without removing a lower portion of the positive photoresist layer. 5. The method of claim 2 , wherein: each of the light emitting diodes comprise a respective active region configured to emit light upon application of a bias voltage thereacross; a matrix portion of the positive photoresist layer adjoining the tapered encirclement portions and continuously extending around each of the light emitting diodes; and the top surface of the positive photoresist layer is formed between a first horizontal plane including top surfaces of the light emitting diodes and a second horizontal plane including the active regions of the light emitting diodes after vertically recessing the positive photoresist layer. 6. The method of claim 1 , wherein the light emitting diodes comprise a respective n-doped compound semiconductor substrate layer having a horizontal cross-sectional area that strictly increases with a distance from the frontside of the backplane.
Package configurations · CPC title
of encapsulations · CPC title
of coatings · CPC title
of electrodes · CPC title
of the light-emitting regions, e.g. non-planar junctions · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.