Light emitting diode device containing a positive photoresist insulating spacer and a conductive sidewall contact and method of making the same

US11784176B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11784176-B2
Application numberUS-202217818822-A
CountryUS
Kind codeB2
Filing dateAug 10, 2022
Priority dateMay 30, 2019
Publication dateOct 10, 2023
Grant dateOct 10, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A light emitting device includes a backplane, an array of light emitting diodes attached to a frontside of the backplane, a positive tone, imageable dielectric material layer, such as a positive photoresist layer, located on the frontside of the backplane and laterally surrounding the array of light emitting diodes, such that sidewalls of the light emitting diodes contacting the positive tone, imageable dielectric material layer have a respective reentrant vertical cross-sectional profile, and at least one common conductive layer located over the positive tone, imageable dielectric material layer and contacting the light emitting diodes.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a light emitting device, comprising: attaching an array of light emitting diodes to a frontside of a backplane; applying a positive tone, imageable dielectric material layer to a frontside of the backplane; vertically recessing the positive tone, imageable dielectric material layer such that a top surface of the positive tone, imageable dielectric material layer is formed below a horizontal plane including top surfaces of the light emitting diodes, wherein sidewalls of the light emitting diodes contacting the positive tone, imageable dielectric material layer have a respective reentrant vertical cross-sectional profile; and forming a transparent conductive layer over the positive tone, imageable dielectric material layer. 2. The method of claim 1 , wherein: the positive tone, imageable dielectric material layer comprises a positive photoresist layer; and sidewalls of the light emitting diodes are reverse-tapered to provide a variable horizontal cross-sectional area that increases with a vertical distance from a frontside surface of the backplane upon attaching the array of light emitting diodes to the frontside of the backplane. 3. The method of claim 2 , wherein vertically recessing the positive photoresist layer comprises performing a blanket exposure process that uncross-links a cross-linked polymer in an upper portion of the positive photoresist layer and subsequently performing a development process. 4. The method of claim 2 , wherein vertically recessing the positive photoresist layer comprises performing a blanket partial ashing process that removes an upper portion of the positive photoresist layer without removing a lower portion of the positive photoresist layer. 5. The method of claim 2 , wherein: each of the light emitting diodes comprise a respective active region configured to emit light upon application of a bias voltage thereacross; a matrix portion of the positive photoresist layer adjoining the tapered encirclement portions and continuously extending around each of the light emitting diodes; and the top surface of the positive photoresist layer is formed between a first horizontal plane including top surfaces of the light emitting diodes and a second horizontal plane including the active regions of the light emitting diodes after vertically recessing the positive photoresist layer. 6. The method of claim 1 , wherein the light emitting diodes comprise a respective n-doped compound semiconductor substrate layer having a horizontal cross-sectional area that strictly increases with a distance from the frontside of the backplane.

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What does patent US11784176B2 cover?
A light emitting device includes a backplane, an array of light emitting diodes attached to a frontside of the backplane, a positive tone, imageable dielectric material layer, such as a positive photoresist layer, located on the frontside of the backplane and laterally surrounding the array of light emitting diodes, such that sidewalls of the light emitting diodes contacting the positive tone, …
Who is the assignee on this patent?
Nanosys Inc
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 10 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).