Nanopyramid sized opto-electronic structure and method for manufacturing of same

Patent metadata

Field	Value
Publication number	US-9444007-B2
Application number	US-201414557674-A
Country	US
Kind code	B2
Filing date	Dec 2, 2014
Priority date	Sep 18, 2012
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

Aspects of the invention provide methods and devices. In one embodiment, the invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, LEDs and transistors. According to the method of the invention nitride semiconductor nanopyramids are grown utilizing a CVD based selective area growth technique. The nanopyramids are grown directly or as core-shell structures.

First claim

The invention claimed is:

1. A method of making a nanopyramid, comprising:
forming a first conductivity type III-V semiconductor core or core seed using CVD at a first temperature, first pressure and first V-III ratio;
forming a first conductivity type III-V semiconductor shell enclosing the core or the core seed of the first conductivity type semiconductor using CVD at a second temperature, second pressure and second V-III ratio; and
forming a first layer of a second conductivity type semiconductor over the shell of the first conductivity type semiconductor to form the nanopyramid;
wherein at least one of the first temperature, first pressure and first V-III ratio is different from at least one of the second temperature, second pressure and second V-III ratio;
wherein the nanopyramid contains a base connected to a dielectric growth mask of the support, a top comprising a sharp point or a mesa having a width smaller than a width of the base, and continuously sloped sidewalls connecting the base to the top; and
wherein:
the first temperature is higher than the second temperature;
the first pressure is lower than the second pressure; and
the first V-III ratio is lower than the second V-III ratio.

2. The method of claim 1 wherein:
forming the first conductivity type III-V semiconductor core or core seed comprises forming the core using paused CVD comprising alternating growth and nitridation steps;
the first V-III ratio during the growth steps in paused CVD is lower than the second V-III ratio; and
a metal organic precursor flow is paused while a nitrogen containing precursor flow is increased during the nitridation steps.

3. The method of claim 1 wherein the nanopyramid is located over the dielectric growth mask containing an opening.

4. The method of claim 3 wherein the first conductivity type semiconductor core or core seed comprises the core which is epitaxially grown on a semiconductor buffer layer exposed in the opening such that the core protrudes from the opening.

5. The method of claim 3 wherein the first conductivity type semiconductor core or core seed comprises the core seed which is nucleated on a semiconductor buffer layer exposed in the opening such that the core seed is located in the opening.

6. The method of claim 1 further comprising forming a second layer of the second conductivity type semiconductor over the first layer of the second conductivity type semiconductor and forming an electrode over the second layer of the second conductivity type.

7. The method of claim 6 further comprising forming at least one feature which reduces or eliminates leakage current at tips of the nanopyramids.

8. The method of claim 7 wherein the at least one feature is selected from at least one of an insulating material tip mask, a hydrogen implanted semiconductor tip region having a higher resistivity than semiconductor sidewalls of the nanopyramids, a plasma damaged semiconductor tip region having a higher resistivity than semiconductor sidewalls of the nanopyramids, a flattened tip in truncated pyramid shaped nanopyramids, and the first conductivity type semiconductor shell having a truncated pyramid shape.

9. The method of claim 6 further comprising forming at least one feature which reduces or eliminates leakage current at bases of the nanopyramids.

10. The method of claim 1 wherein:
the first temperature is 1000 to 1200° C. and the second temperature is 800 to 1000° C.;
the first pressure is 50 to 100 torr and the second pressure is 100 to 500 torr; and
the first III-V ratio is 5 to 10 and the second V-III ratio is 10,000 to 15,000.

Assignees

• Glo Ab

Inventors

• Kryliouk Olga
• Gardner Nathan
• Vescovi Giuliano Portilho

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10H20/813

  having a plurality of light-emitting regions, e.g. multi-junction LEDs or light-emitting devices having photoluminescent regions within the bodies · CPC title

• H10H20/812

  within the light-emitting regions, e.g. having quantum confinement structures · CPC title

• H10H20/01335 Primary

  the light-emitting regions comprising nitride materials · CPC title