Semiconductor package having thin substrate and method of making the same

Patent metadata

Field	Value
Publication number	US-11784141-B2
Application number	US-202217960700-A
Country	US
Kind code	B2
Filing date	Oct 5, 2022
Priority date	Dec 20, 2017
Publication date	Oct 10, 2023
Grant date	Oct 10, 2023

Abstract

A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulaton process so as to form a plurality of semiconductor packages.

First claim

The invention claimed is:

1. A semiconductor package comprising:
a semiconductor substrate having a front surface and a back surface opposite the front surface of the semiconductor substrate;
a first metal layer having a front surface and a back surface opposite the front surface of the first metal layer, the front surface of the first metal layer being directly attached to the back surface of the semiconductor substrate;
an adhesive layer having a front surface and a back surface opposite the front surface of the adhesive layer, the front surface of the adhesive layer being directly attached to the back surface of the first metal layer;
a second metal layer having a front surface and a back surface opposite the front surface of the second metal layer, the front surface of the second metal layer being directly attached to the back surface of the adhesive layer;
a rigid supporting layer having a front surface and a back surface opposite the front surface of the rigid supporting layer, the front surface of the rigid supporting layer being directly attached to the back surface of the second metal layer; and
a plurality of contact pads attached to the front surface of the semiconductor substrate;
wherein a thickness of the semiconductor substrate is equal to or less than 75 microns;
wherein a thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate;
wherein an edge surface of the first metal layer and an edge surface of the adhesive layer are aligned and coplanar;
wherein the semiconductor package is a common-drain metal-oxide-semiconductor field-effect transistor (MOSFET) chip scale package (CSP) for battery protection application;
wherein two gates and two sources are on a front surface of the common-drain MOSFET CSP; and
wherein a common-drain is on a back surface of the common-drain MOSFET CSP.

2. The semiconductor package of claim 1 , wherein a Young's modulus of an entirety of the rigid supporting layer is in a range from 50% to 150% of a Young's modulus of the semiconductor substrate; and wherein a coefficient of thermal expansion (CTE) of the entirety of the rigid supporting layer is in a range from 50% to 250% of the CTE of the semiconductor substrate.

3. The semiconductor package of claim 1 , wherein an entirety of the rigid supporting layer is made of a single crystal silicon material or a poly-crystal silicon material fabricated from a reclaimed silicon wafer.

4. The semiconductor package of claim 1 , wherein an entirety of the rigid supporting layer is made of an amorphous glass material.

5. The semiconductor package of claim 1 , wherein an entirety of the first metal layer is made of a material selected from the group consisting of aluminum, nickel, and gold; and wherein an entirety of the second metal layer is made of a material selected from the group consisting of titanium, nickel, and silver.

6. The semiconductor package of claim 1 , wherein a thickness of the first metal layer is in a range from 1 micron to 5 microns.

7. The semiconductor package of claim 1 , wherein a thickness of the second metal layer is in a range from 30 microns to 100 microns.

8. The semiconductor package of claim 1 , wherein a thickness of the rigid supporting layer is in a range from 75 microns to 500 microns.

9. The semiconductor package of claim 1 , wherein the adhesive layer comprises electrically conductive adhesive.

10. A method for fabricating a plurality of semiconductor packages, the method comprising the steps of:
providing a device wafer comprising
a semiconductor substrate having a front surface and a back surface opposite the front surface of the semiconductor substrate;
a first metal layer having a front surface and a back surface opposite the front surface of the first metal layer, the front surface of the first metal layer being directly attached to the back surface of the semiconductor substrate; and
a plurality of contact pads attached to the front surface of the semiconductor substrate;

providing a supporting wafer comprising
a second metal layer having a front surface and a back surface opposite the front surface of the second metal layer; and
a rigid supporting layer having a front surface and a back surface opposite the front surface of the rigid supporting layer, the front surface of the rigid supporting layer being directly attached to the back surface of the second metal layer;

attaching the supporting wafer to the device wafer via an adhesive layer, the adhesive layer having a front surface and a back surface opposite the front surface of the adhesive layer, the front surface of the adhesive layer being directly attached to the back surface of the first metal layer, and the front surface of the second metal layer being directly attached to the back surface of the adhesive layer; and
applying a singulation process;
wherein a thickness of the semiconductor substrate is equal to or less than 75 microns;
wherein a thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate;
wherein an edge surface of the first metal layer and an edge surface of the adhesive layer are aligned and coplanar;
wherein each of the plurality of semiconductor packages is a common-drain metal-oxide-semiconductor field-effect transistor (MOSFET) chip scale package (CSP) for battery protection application;
wherein two gates and two sources are on a front surface of the common-drain MOSFET CSP; and
wherein a common-drain is on a back surface of the common-drain MOSFET CSP.

11. The method of claim 10 , wherein a thickness of the first metal layer is in a range from 1 micron to 5 microns.

12. The method of claim 10 , wherein a thickness of the second metal layer is in a range from 30 microns to 100 microns.

13. The method of claim 10 , wherein a thickness of the rigid supporting layer is in a range of 75 microns to 500 microns.

14. The method of claim 10 , wherein the adhesive layer comprises electrically conductive adhesive.

15. The method of claim 10 , wherein a Young's modulus of an entirety of the rigid supporting layer is in a range from 50% to 150% of a Young's modulus of the semiconductor substrate; and wherein a coefficient of thermal expansion (CTE) of the entirety of the rigid supporting layer is in a range from 50% to 250% of the CTE of the semiconductor substrate.

16. The method of claim 10 , wherein an entirety of the rigid supporting layer is made of a single crystal silicon material or a poly-crystal silicon material fabricated from a reclaimed silicon wafer.

17. The method of claim 10 , wherein an entirety of the rigid supporting layer is made of an amorphous glass material.

18. The method of claim 10 , wherein an entirety of the first metal layer is made of a material selected from the group consisting of aluminum, nickel, and gold; and wherein an entirety of the second metal layer is made of a material selected from the group consisting of titanium, nickel, and silver.

Assignees

• Alpha & Omega Semiconductor Int Lp

Inventors

• Lu Jun
• Wang Long-Ching
• Bobde Madhur
• Chen Bo
• Zhou Shuhua

Classifications

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/936

  Multiple bond pads having different shapes · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title