Shielded semiconductor package with open terminal and methods of making

Patent metadata

Field	Value
Publication number	US-11784133-B2
Application number	US-202017136197-A
Country	US
Kind code	B2
Filing date	Dec 29, 2020
Priority date	Dec 14, 2018
Publication date	Oct 10, 2023
Grant date	Oct 10, 2023

Abstract

A semiconductor device has a substrate. An electrical component is disposed over a surface of the substrate. An encapsulant is deposited over the electrical component and substrate. A portion of the surface of the substrate remains exposed from the encapsulant. A shielding layer is formed over the encapsulant. A portion of the shielding layer is removed to expose the portion of the surface of the substrate.

First claim

What is claimed:

1. A semiconductor device, comprising:
a substrate including a plurality of contact pads formed over a portion of a surface of the substrate;
an electrical component disposed over the surface of the substrate;
an encapsulant deposited over the electrical component and substrate, wherein the portion of the surface of the substrate remains exposed from the encapsulant; and
a shielding layer formed over the encapsulant, wherein the portion of the surface of the substrate is exposed from the shielding layer.

2. The semiconductor device of claim 1 , further including a laser disposed over the portion of the surface of the substrate.

3. The semiconductor device of claim 1 , further including a mask disposed over the portion of the surface of the substrate.

4. The semiconductor device of claim 1 , further including a jig with a tab of the jig disposed over the portion of the surface of the substrate.

5. The semiconductor device of claim 4 , further including an insulating layer physically contacting the tab of the jig and the portion of the surface of the substrate.

6. The semiconductor device of claim 1 , wherein the portion of the surface of the substrate includes a terminal or socket.

7. A semiconductor device, comprising:
a substrate;
an electrical component disposed over a surface of the substrate;
an encapsulant deposited over the electrical component and substrate, wherein a portion of the surface of the substrate remains exposed from the encapsulant;
a jig including a tab of the jig disposed over the portion of the surface of the substrate; and
a shielding layer formed over the encapsulant and jig, wherein the shielding layer is formed on a side surface of the encapsulant and a side surface of the substrate.

8. The semiconductor device of claim 7 , further including an insulating layer disposed on the tab of the jig.

9. The semiconductor device of claim 8 , wherein the insulating layer is disposed in physical contact with the tab of the jig and the portion of the surface of the substrate.

10. The semiconductor device of claim 8 , wherein the insulating layer covers an entire surface of the jig.

11. The semiconductor device of claim 8 , wherein the insulating layer is a polyimide layer.

12. The semiconductor device of claim 7 , wherein the portion of the surface of the substrate includes a terminal or socket.

13. The semiconductor device of claim 7 , wherein the portion of the surface of the substrate includes a contact pad.

14. A semiconductor device, comprising:
a substrate;
an electrical component disposed over the substrate;
an encapsulant deposited over the electrical component and substrate, wherein a portion of the substrate remains exposed from the encapsulant; and
a shielding layer formed over the encapsulant, wherein the shielding layer physically contacts the substrate.

15. The semiconductor device of claim 14 , further including a laser disposed over the portion of the substrate.

16. The semiconductor device of claim 14 , further including a mask disposed over the portion of the substrate.

17. The semiconductor device of claim 14 , further including a jig including a tab of the jig disposed over the portion of the substrate.

18. The semiconductor device of claim 17 , further including an insulating layer disposed between the tab of the jig and the portion of the substrate.

19. The semiconductor device of claim 14 , wherein the portion of the substrate includes a contact pad.

20. A semiconductor device, comprising:
a substrate;
an encapsulant deposited over a first portion of the substrate; and
a shielding layer formed over the encapsulant, wherein a second portion of the substrate including a plurality of contact pads is exposed from the encapsulant and shielding layer.

21. The semiconductor device of claim 20 , further including a contact pad disposed on the second portion of the substrate.

22. The semiconductor device of claim 21 , further including a semiconductor package disposed adjacent to the substrate outside the encapsulant, wherein the semiconductor package includes an interconnect structure connected to the contact pad.

23. The semiconductor device of claim 21 , wherein the contact pad is formed on a first surface of the substrate, and the encapsulant is deposited over the first surface of the substrate.

24. The semiconductor device of claim 20 , further including a radio frequency (RF) electrical component disposed over the substrate within the encapsulant.

25. The semiconductor device of claim 20 , wherein a top surface and every side surface of the encapsulant are completely covered by the shielding layer.

Assignees

• Stats Chippac Pte Ltd

Inventors

• Kim Changoh
• Koo Kyowang
• Cho Sungwon
• Choi Bongwoo
• Lee Jiwon

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/016

  using moulds · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W74/012

  of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills · CPC title