Semiconductor device and method of forming shielding layer over semiconductor die mounted to TSV interposer

Patent metadata

Field	Value
Publication number	US-9685403-B2
Application number	US-201414331050-A
Country	US
Kind code	B2
Filing date	Jul 14, 2014
Priority date	Mar 8, 2011
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A semiconductor device has a plurality of conductive vias formed partially through a substrate. A conductive layer is formed over the substrate and electrically connected to the conductive vias. A semiconductor die is mounted over the substrate. An encapsulant is deposited over the semiconductor die and substrate. A trench is formed through the encapsulant around the semiconductor die. A shielding layer is formed over the encapsulant. The trench is formed partially through the substrate and the shielding layer is formed in the trench partially through the substrate. An insulating layer can be formed in the trench prior to forming the shielding layer. A portion of the substrate is removed to expose the conductive vias. An interconnect structure is formed over the substrate opposite the semiconductor die. The interconnect structure is electrically connected to the conductive vias. The shielding layer is electrically connected to the interconnect structure.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a first substrate;
forming a plurality of conductive vias into the first substrate;
providing a second substrate;
disposing a semiconductor die over the first substrate and electrically connected to a first conductive via of the plurality of conductive vias;
depositing an encapsulant over the first substrate and semiconductor die;
forming a trench through the encapsulant to expose a second conductive via of the plurality of conductive vias;
forming a shielding layer over the encapsulant and extending into the trench to contact the second conductive via;
planarizing a surface of the first substrate opposite the semiconductor die with the plurality of conductive vias;
forming a build-up interconnect structure over the surface of the first substrate; and
disposing the first substrate over the second substrate with the semiconductor die and shielding layer electrically coupled to the second substrate through the plurality of conductive vias and the build-up interconnect structure.

2. The method of claim 1 , further including forming a conductive bump over the build-up interconnect structure with the semiconductor die electrically coupled to the second substrate through the conductive bump.

3. The method of claim 1 , further including forming a seed layer into the first substrate between the shielding layer and encapsulant.

4. The method of claim 1 , further including forming an insulating layer between the shielding layer and encapsulant.

5. A method of making a semiconductor device, comprising:
providing a first substrate;
disposing a semiconductor die over the first substrate;
depositing an encapsulant over the first substrate and semiconductor die;
forming a trench through the encapsulant with a closed end that extends into the first substrate;
forming a shielding layer in the trench and over the semiconductor die;
planarizing a surface of the first substrate opposite the semiconductor die to open the closed end of the trench; and
disposing the first substrate over a second substrate.

6. The method of claim 5 , further including forming a seed layer over the semiconductor die and into the trench prior to forming the shielding layer.

7. The method of claim 5 , further including forming an insulating layer in the trench.

8. The method of claim 5 , further including forming a build-up interconnect structure including an insulating layer and a redistribution layer (RDL) over the first substrate opposite the semiconductor die prior to disposing the first substrate over the second substrate.

9. The method of claim 8 , further including electrically connecting the build-up interconnect structure to the shielding layer through the first substrate.

10. The method of claim 5 , further including depositing a conductive paste between the shielding layer and the second substrate.

11. A method of making a semiconductor device, comprising:
providing a first substrate;
disposing a semiconductor die over the first substrate;
forming a trench into the first substrate;
forming a shielding layer over the semiconductor die and into the trench;
backgrinding the first substrate opposite the semiconductor die to expose the shielding layer;
disposing the first substrate over a second substrate; and
depositing a conductive paste extending from the second substrate to the shielding layer.

12. The method of claim 11 , further including:
depositing an encapsulant over the semiconductor die and first substrate; and
forming the trench through the encapsulant.

13. The method of claim 12 , further including forming a seed layer between the shielding layer and encapsulant.

14. The method of claim 12 , further including forming an insulating layer between the shielding layer and encapsulant.

15. The method of claim 11 , further including forming the shielding layer around a peripheral area of the semiconductor die.

16. A method of making a semiconductor device, comprising:
providing a substrate;
forming a plurality of conductive vias through a first surface of the substrate;
disposing a semiconductor die over the first surface of the substrate;
disposing an encapsulant over the semiconductor die;
forming a trench through the encapsulant and into the substrate;
forming a shielding layer over the encapsulant and into the trench; and
backgrinding the substrate to expose the plurality of conductive vias and shielding layer.

17. The method of claim 16 , further including forming an interconnect structure over a second surface of the substrate opposite the first surface.

18. The method of claim 17 , further including electrically connecting the shielding layer to the interconnect structure.

19. The method of claim 18 , wherein electrically connecting includes forming a redistribution layer.

Assignees

• Stats Chippac Ltd
• Stats Chippac Pte Ltd

Inventors

• Pagaila Reza A

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/0198

  batch processes · CPC title