Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Patent metadata

Field	Value
Publication number	US-9768155-B2
Application number	US-201514745203-A
Country	US
Kind code	B2
Filing date	Jun 19, 2015
Priority date	Dec 12, 2008
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
disposing the semiconductor die over a carrier with an active surface of the semiconductor die oriented toward the carrier;
depositing an encapsulant over the carrier and around the semiconductor die to form a reconstituted panel;
removing the reconstituted panel from the carrier;
forming a first insulating layer over a surface of the encapsulant and the active surface of the semiconductor die;
forming a conductive via through the first insulating layer;
forming an opening through the encapsulant extending to the conductive via after forming the conductive via; and
depositing a conductive material in the opening.

2. The method of claim 1 , wherein depositing the conductive material in the opening forms a bump.

3. The method of claim 1 , further including forming an interconnect structure over the first insulating layer and semiconductor die.

4. The method of claim 1 , further including removing a portion of the encapsulant to make a surface of the encapsulant coplanar with the semiconductor die.

5. The method of claim 1 , further including forming a second insulating layer over the encapsulant and semiconductor die.

6. The method of claim 1 , further including stacking a plurality of semiconductor devices electrically connected through the conductive via and conductive material.

7. A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing an encapsulant around the semiconductor die;
forming a first insulating layer over a surface of the encapsulant;
forming a first interconnect structure including a plurality of adjacent conductive vias through the first insulating layer; and
forming an opening through the encapsulant with each of the plurality of adjacent conductive vias in the opening.

8. The method of claim 7 , further including depositing a conductive material in the opening and contacting each of the plurality of adjacent conductive vias.

9. The method of claim 8 , wherein forming the first interconnect structure further includes forming a bump over the adjacent conductive vias opposite the conductive material.

10. The method of claim 7 , further including removing a portion of the encapsulant over the semiconductor die.

11. The method of claim 7 , further including forming a second insulating layer over the encapsulant and semiconductor die.

12. The method of claim 7 , further including forming a second interconnect structure over the first interconnect structure and semiconductor die.

13. The method of claim 7 , further including stacking a plurality of semiconductor devices electrically connected through the first interconnect structure.

14. A method of making a semiconductor device, comprising:
providing a substrate;
depositing an encapsulant around the substrate;
forming a first insulating layer over a surface of the encapsulant;
forming a conductive layer over the first insulating layer;
forming an opening through the encapsulant extending to the conductive layer; and
depositing a conductive material in the opening after forming the conductive layer.

15. The method of claim 14 , wherein forming the conductive layer includes forming a plurality of adjacent conductive vias through the first insulating layer.

16. The method of claim 14 , further including removing a portion of the encapsulant over the substrate.

17. The method of claim 14 , further including forming a second insulating layer over the encapsulant and substrate.

18. The method of claim 14 , further including forming an interconnect structure over the encapsulant and substrate.

19. The method of claim 14 , further including stacking a plurality of semiconductor devices electrically connected through the conductive layer and conductive material.

Assignees

• Stats Chippac Ltd
• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian
• Chen Kang
• Yoon Seung Wook

Classifications

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title