Wrap around cross-couple contact structure with enhanced gate contact size

Patent metadata

Field	Value
Publication number	US-11784125-B2
Application number	US-202117375670-A
Country	US
Kind code	B2
Filing date	Jul 14, 2021
Priority date	Jul 14, 2021
Publication date	Oct 10, 2023
Grant date	Oct 10, 2023

Abstract

A cross-couple contact structure is provided that is located on, and physically contacts, a topmost surface of a functional gate structure that is located laterally adjacent to a gate cut region. The cross-couple contact structure extends into the laterally adjacent gate cut region and physically contacts a sidewall of the functional gate structure, an upper portion of a first sidewall of a dielectric plug that is present in the gate cut region, and an upper surface of a dielectric liner that is located on a lower portion of the first sidewall of the dielectric plug.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a dielectric plug located in a gate cut region and having a first sidewall, a bottom wall, and a second sidewall opposite the first sidewall;
a dielectric liner located in the gate cut region and on an entirety of the second sidewall of the dielectric plug, the bottom wall of the dielectric plug, and a lower portion of the first sidewall of the dielectric plug; and
a cross-couple contact structure located on, and physically contacting, a topmost surface of a functional gate structure that is located laterally adjacent to the gate cut region, wherein the cross-couple contact structure extends into the gate cut region and physically contacts a sidewall of the functional gate structure, an upper portion of the first sidewall of the dielectric plug, and an upper surface of the dielectric liner that is located on the lower portion of the first sidewall of the dielectric plug.

2. The semiconductor structure of claim 1 , wherein a first vertical extending portion of the dielectric liner is located entirely on the second sidewall of the dielectric plug, and a second vertical extending portion of the dielectric liner is located on the lower portion of the first sidewall of the dielectric plug, wherein the first vertical extending portion has a height that is greater than the second vertical extending portion.

3. The semiconductor structure of claim 2 , wherein the first vertical extending portion of the dielectric liner has a topmost surface that is coplanar with a topmost surface of each of the dielectric plug and the cross-couple contact structure.

4. The semiconductor structure of claim 1 , wherein the dielectric liner is composed of a first dielectric material and the dielectric plug is composed of a second dielectric material that is compositionally different from the first dielectric material.

5. The semiconductor structure of claim 4 , wherein the first dielectric material is a silicon nitride based dielectric material, and the second dielectric material is a silicon carbon based dielectric material.

6. The semiconductor structure of claim 1 , wherein the first sidewall of the dielectric plug faces a cut semiconductor channel-containing structure, and the second sidewall of the dielectric plug faces a non-cut semiconductor channel-containing structure.

7. The semiconductor structure of claim 6 , wherein the cut semiconductor channel-containing structure is located in a PFET device region, and the non-cut semiconductor channel-containing structure is located in an NFET device region.

8. The semiconductor structure of claim 6 , wherein a portion of the cut semiconductor channel-containing structure is tucked beneath the functional gate structure.

9. The semiconductor structure of claim 6 , wherein the cut semiconductor channel-containing structure is a cut semiconductor fin, and the non-cut semiconductor channel-containing structure is a non-cut semiconductor fin.

10. The semiconductor structure of claim 1 , wherein the first sidewall of the dielectric plug faces a first non-semiconductor channel-containing structure that has a portion tucked under the functional gate structure and present in a PFET device region, and the second sidewall of the dielectric plug faces a non-cut semiconductor channel-containing structure that is present in an NFET device region.

11. The semiconductor structure of claim 1 , wherein the first and second sidewalls of the dielectric plug are tapered sidewalls that increase upward from a bottommost surface of the dielectric plug to a topmost surface of the dielectric plug.

12. The semiconductor structure of claim 1 , wherein the functional gate structure contacts a topmost surface and one sidewall surface of a cut semiconductor channel-containing structure, and the other sidewall surface of the cut semiconductor channel-containing structure contacts an outermost sidewall of the dielectric liner.

13. The semiconductor structure of claim 1 , wherein the gate cut region is located over a shallow trench isolation structure that is located on a substrate.

14. A method of forming a semiconductor structure, the method comprising:
forming a gate cut region between two laterally adjacent semiconductor channel-containing structures, wherein one of the semiconductor channel-containing structures is a present in an NFET device region and the other of the semiconductor channel-containing structures is located in a PFET device region;
forming a bilayer dielectric material structure in the gate cut region, wherein the bilayer dielectric material structure comprises a dielectric plug having a first sidewall, a bottom wall, and a second sidewall opposite the first sidewall, and a dielectric layer lining the first sidewall, the bottom wall, and the second sidewall of the dielectric plug, and wherein the first sidewall of the dielectric plug faces the semiconductor channel-containing structure present in the PFET device region;
forming a functional gate structure on the semiconductor channel-containing structure in at least the PFET device region;
forming a cross-couple contact region that physically exposes a topmost surface of the functional gate structure present in the PFET device region, wherein during the forming of the cross-couple contact region an upper portion of the dielectric layer that is located the first sidewall of the dielectric plug is removed; and
forming a cross-couple contact structure in the cross-couple contact region, wherein the cross-couple contact structure physically contacts a topmost surface of the functional gate structure present in the PFET device region, and extends into the gate cut region so that the cross-couple contact structure physically contacts a sidewall of the functional gate structure, an upper portion of the first sidewall of the dielectric plug, and an upper surface of the dielectric layer that is located on a lower portion of the first sidewall of the dielectric plug.

15. The method of claim 14 , wherein the semiconductor channel-containing structure in the PFET device region is a cut semiconductor channel-containing structure.

16. The method of claim 15 , wherein a portion of the cut semiconductor channel-containing structure is tucked beneath the functional gate structure in the PFET device region.

17. The method of claim 15 , wherein the cut semiconductor channel-containing structure is a cut semiconductor fin.

18. The method of claim 14 , wherein the dielectric layer is composed of a first dielectric material and the dielectric plug is composed of a second dielectric material that is compositionally different from the first dielectric material.

19. The method of claim 18 , wherein first dielectric material is a silicon nitride based dielectric material, and the second dielectric material is a silicon carbon based dielectric material.

20. The method of claim 18 , wherein the forming the cross-couple contact region comprises an etching process that removes the first dielectric material selective to the second dielectric material.

Assignees

• IBM

Inventors

• Xie Ruilong
• Cheng Kangguo
• Park Chanro
• Frougier Julien

Classifications

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title