Merged source/drain and gate contacts in SRAM bitcell

Patent metadata

Field	Value
Publication number	US-9406616-B2
Application number	US-201414561359-A
Country	US
Kind code	B2
Filing date	Dec 5, 2014
Priority date	Dec 5, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A method of forming a semiconductor device with uniform regular shaped gate contacts and the resulting device are disclosed. Embodiments include forming first and second gate electrodes adjacent one another on a substrate; forming at least one trench silicide (TS) on the substrate between the first and second gate electrodes; forming a gate contact on the first gate electrode, the gate contact having a regular shape; forming a source/drain contact on a trench silicide between the first and second gate electrodes, wherein an upper portion of the source/drain contact overlaps an upper portion of the gate contact.

First claim

What is claimed is:

1. A method comprising:
forming first and second gate electrodes adjacent one another on a substrate;
forming at least one trench silicide (TS) on the substrate between the first and second gate electrodes;
forming a gate contact on the first gate electrode, the gate contact having a regular shape;
forming a source/drain contact on a trench silicide between the first and second gate electrodes, wherein a bottom of the source/drain contact is the same width as the trench silicide, and a bottom of the gate contact is the same width as the gate electrode; and
forming a sloped profile of the gate contact and the source/drain contact, such that an upper portion of the gate contact is wider than the bottom of the gate contact and an upper portion of the source/drain contact is wider than the bottom of the source/drain contact, wherein the upper portion of the source/drain contact overlaps the upper portion of the gate contact.

2. The method according to claim 1 , wherein the regular shape comprises a square.

3. The method according to claim 1 , wherein the source/drain contact comprises a self-aligned contact.

4. The method according to claim 1 , further comprising forming a second source/drain contact on a second TS between the first and second gate electrodes and a second gate contact having the regular shape on the second gate electrode, wherein an upper portion of the second source/drain contact overlaps an upper portion of the second gate contact.

5. The method according to claim 4 , wherein the overlapping first gate contact and first source/drain contact and the overlapping second gate contact and second source/drain contact cross-couple the first and second gate electrodes.

6. The method according to claim 1 , wherein a width of a bottom surface of the gate contact corresponds to a width of each of the first and second gate electrodes.

7. The method according to claim 1 , further comprising:
forming additional gate electrodes parallel to and spaced from the first and second gate electrodes;
forming at least one additional TS between each pair of adjacent gate electrodes;
forming at least one additional gate contact having the regular shape on at least one additional gate electrode; and
forming at least one additional source/drain contact on one or more of the at least one additional TSs.

8. The method according to claim 7 , further comprising connecting one or more of the additional source/drain contacts and the additional gate contacts to a first metal (M1) layer above the gate electrodes and the TSs.

9. A device comprising:
first and second gate electrodes adjacent one another on a substrate;
at least one trench silicide (TS) on the substrate between the first and second gate electrodes;
a gate contact on the first gate electrode, the gate contact having a regular shape;
a source/drain contact on a trench silicide between the first and second gate electrodes, wherein a bottom of the source/drain contact is the same width as the trench silicide, and a bottom of the gate contact is the same width as the gate electrode; and
wherein the gate contact and the source/drain contact have sloped profiles, such that an upper portion of the gate contact is wider than the bottom of the gate contact and an upper portion of the source/drain contact is wider than the bottom of the source/drain contact, and the upper portion of the source/drain contact overlaps the upper portion of the gate contact.

10. The device according to claim 9 , wherein the regular shape comprises a square.

11. The device according to claim 9 , wherein the source/drain contact comprises a self-aligned contact.

12. The device according to claim 9 , further comprising a second source/drain contact on a second TS between the first and second gate electrodes and a second gate contact having the regular shape on the second gate electrode, wherein an upper portion of the second source/drain contact overlaps an upper portion of the second gate contact.

13. The device according to claim 12 , wherein the overlapping first gate contact and first source/drain contact and the overlapping second gate contact and second source/drain contact cross-couple the first and second gate electrodes.

14. The device according to claim 9 , wherein a width of a bottom surface of the gate contact corresponds to a width of each of the first and second gate electrodes.

15. The device according to claim 9 , further comprising:
additional gate electrodes parallel to and spaced from the first and second gate electrodes;
at least one additional TS between each pair of adjacent gate electrodes;
at least one additional gate contact having the regular shape on at least one additional gate electrode; and
at least one additional source/drain contact on one or more of the at least one additional TSs.

16. The device according to claim 15 , further comprising one or more of the additional source/drain contacts and the additional gate contacts being connected to a first metal (M1) layer above the gate electrodes and the TSs.

17. A method comprising:
forming plural parallel and equally spaced gate electrodes on a substrate;
forming trench silicides (TSs) on the substrate between pairs of adjacent gate electrodes;
forming gate contacts on plural gate electrodes, the gate contacts having a uniform, regular shape, where a width of a bottom surface of each gate contact corresponds to a width of each gate electrode;
forming source/drain contacts on plural TSs, wherein an upper portion of a first source/drain contact on a first TS overlaps an upper portion of a first gate contact on an adjacent first gate electrode, and an upper portion of a second source/drain contact on the first TS overlaps an upper portion of a second gate contact on a second gate electrode adjacent the first TS, cross-coupling the first and second gate electrodes,
wherein the upper portion of the first source/drain contact has a width greater than the width of a bottom surface of the first source/drain contact and the upper portion of the second source/drain contact has a width greater than the width of a bottom surface of the second source/drain contact.

18. The method according to claim 17 , wherein the regular shape comprises a square.

19. The method according to claim 17 , wherein the source/drain contacts comprise self-aligned contacts.

20. The method according to claim 17 , further comprising connecting one or more additional source/drain contacts and additional gate contacts to a first metal (M1) layer above the gate electrodes and the TSs.

21. The method according to claim 17 , wherein the upper portion of the first gate contact is wider than the bottom surface of the first gate contact and the upper portion of the second gate contact is wider than the bottom surface of the second gate contact.

Assignees

• Globalfoundries Inc

Inventors

• Woo Youngtag
• Kim Ryan Ryoung-Han

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title