Covers for semiconductor package components

Patent metadata

Field	Value
Publication number	US-11784103-B2
Application number	US-202017116936-A
Country	US
Kind code	B2
Filing date	Dec 9, 2020
Priority date	Dec 9, 2020
Publication date	Oct 10, 2023
Grant date	Oct 10, 2023

Abstract

In some examples, a semiconductor package comprises a semiconductor die; an operational component on an active surface of the semiconductor die; and a cover coupled to the active surface of the semiconductor die and covering the operational component. The cover comprises a monolithic structure including a vertical portion and a horizontal portion. A hollow area is between the cover and the operational component. The package also includes a mold compound covering the semiconductor die and the cover.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a semiconductor die;
an operational component on an active surface of the semiconductor die;
a cover coupled to the active surface of the semiconductor die and covering the operational component, the cover comprising a monolithic structure including a vertical portion and a horizontal portion, a hollow area between the cover and the operational component; and
a mold compound covering the semiconductor die and the cover, wherein the cover comprises metal, and wherein the cover couples to the semiconductor die with solder.

2. The semiconductor package of claim 1 , wherein the cover comprises metal, and wherein the cover is coupled to the active surface with a metal or metal alloy.

3. The semiconductor package of claim 1 , wherein the cover has a depth of no more than 1 millimeter.

4. The semiconductor package of claim 1 , wherein the hollow area is inert.

5. The semiconductor package of claim 1 , wherein a portion of the cover is vertically aligned with a center of the semiconductor package.

6. The semiconductor package of claim 1 , wherein the operational component is hermetically sealed.

7. The semiconductor package of claim 1 , wherein the cover has a slanted or stepped outer surface.

8. A semiconductor package, comprising:
a semiconductor die including a precision circuit;
a cover coupled to the semiconductor die over the precision circuit; and
a mold compound covering a top and side surfaces of the cover, the cover creating a cavity between the mold compound and the semiconductor die, wherein the cover comprises metal, and wherein the cover couples to the semiconductor die with solder.

9. The semiconductor package of claim 8 , wherein a portion of the cover is vertically aligned with a center of the semiconductor die.

10. The semiconductor package of claim 8 , further comprising a hollow area between the cover and the semiconductor die.

11. The semiconductor package of claim 10 , wherein the hollow area is inert.

12. The semiconductor package of claim 8 , wherein the cover provides a hermetic seal to the precision circuit.

13. The semiconductor package of claim 8 , wherein the mold compound abuts a top surface of the cover and a side surface of the cover.

14. The semiconductor package of claim 8 , wherein the precision circuit closer to a center of the semiconductor die than to an edge of the semiconductor die.

15. The semiconductor package of claim 8 , wherein the cavity includes a vertical dimension less than or equal to 1 millimeter from the semiconductor die to the cover.

Assignees

• Texas Instruments Inc

Inventors

• Koduri Sreenivasan Kalyani
• Stark Leslie Edward

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W70/40

  Leadframes · CPC title

• H10W74/124 Primary

  the encapsulations having cavities other than that occupied by chips · CPC title

• H10W74/01

  Manufacture or treatment · CPC title