Semiconductor package

Patent metadata

Field	Value
Publication number	US-11776941-B2
Application number	US-202117357378-A
Country	US
Kind code	B2
Filing date	Jun 24, 2021
Priority date	Oct 19, 2020
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

A semiconductor package includes a package substrate, a connection substrate on the package substrate, a first image sensor chip on the connection substrate, a second image sensor chip on the connection substrate, the second image sensor chip being horizontally spaced apart from the first image sensor chip, and a memory chip disposed on the package substrate and electrically connected to the first image sensor chip through the connection substrate. A distance between the first image sensor chip and the second image sensor chip is less than a thickness of the first image sensor chip.

First claim

What is claimed is:

1. A semiconductor package comprising:
a package substrate;
a connection substrate on the package substrate;
a first image sensor chip on the connection substrate;
a second image sensor chip on the connection substrate, the second image sensor chip being horizontally spaced apart from the first image sensor chip;
a plurality of lenses including first and second lenses vertically overlapping the first and second image sensor chips respectively;
a lens holder supporting the plurality of lenses; and
a memory chip disposed on the package substrate and electrically connected to the first image sensor chip through the connection substrate,
wherein the lens holder comprises sidewalls extending vertically from a top surface of the connection substrate and an upper portion extending horizontally from the sidewalls and holding the plurality of lenses such that the lens holder and the plurality of lenses together with the connection substrate enclose the first and second image sensor chips,
wherein the upper portion of the lens holder is disposed at the same height as the plurality of lenses,
wherein a portion of the lens holder is interposed between the plurality of lenses,
wherein the portion of the lens holder contacts the plurality of lenses, and
wherein a distance between the first image sensor chip and the second image sensor chip is less than a vertical thickness of the first image sensor chip.

2. The semiconductor package of claim 1 , wherein the distance between the first image sensor chip and the second image sensor chip is less than a vertical thickness of the connection substrate.

3. The semiconductor package of claim 1 , wherein the distance between the first image sensor chip and the second image sensor chip is in a range between 30 μm and 50 μm.

4. The semiconductor package of claim 1 , wherein a vertical thickness of the connection substrate is less than the vertical thickness of the first image sensor chip.

5. The semiconductor package of claim 1 , wherein a vertical thickness of the connection substrate is in a range between 80 μm and 120 μm.

6. The semiconductor package of claim 1 , wherein the connection substrate has first pads on a first surface facing the package substrate and has second pads on a second surface facing the first image sensor chip, and
wherein a pitch of the second pads is less than a pitch of the first pads.

7. The semiconductor package of claim 1 , wherein the connection substrate comprises: a support layer; a through-electrode vertically penetrating the support layer; and a redistribution layer disposed on the support layer and the through-electrode.

8. The semiconductor package of claim 7 , wherein the support layer includes silicon.

9. The semiconductor package of claim 1 , further comprising:
a logic chip mounted on the package substrate and electrically connected to the first image sensor chip through the connection substrate,
wherein the distance between the first image sensor chip and the second image sensor chip is less than a distance between the memory chip and the logic chip.

10. A semiconductor package comprising:
a package substrate;
a connection substrate disposed on the package substrate, the connection substrate comprising: a support layer; a through-electrode vertically penetrating the support layer; and a redistribution layer electrically connected to the through-electrode;
a first image sensor chip mounted on the redistribution layer;
a second image sensor chip mounted on the redistribution layer and horizontally spaced apart from the first image sensor chip;
a first semiconductor chip disposed on the package substrate and electrically connected to the first image sensor chip through the connection substrate;
a second semiconductor chip disposed on the package substrate and electrically connected to the first image sensor chip through the connection substrate; and
a lens holder supporting first and second lenses vertically overlapping the first and second image sensor chips respectively,
wherein the lens holder comprises sidewalls extending vertically from a top surface of the connection substrate and an upper portion extending horizontally from the sidewalls and holding the first and second lenses such that the lens holder and the first and second lenses together with the connection substrate enclose the first and second image sensor chips,
wherein the upper portion of the lens holder is disposed at the same height as the first and second lenses,
wherein a portion of the lens holder is interposed between the first and second lenses,
wherein the portion of the lens holder contacts the first and second lenses, and
wherein a distance between the first image sensor chip and the second image sensor chip is less than a distance between the first semiconductor chip and the second semiconductor chip.

11. The semiconductor package of claim 10 , wherein the first semiconductor chip includes a logic chip, and
wherein the second semiconductor chip includes a memory chip.

12. The semiconductor package of claim 10 , wherein the distance between the first image sensor chip and the second image sensor chip is less than a vertical thickness of the connection substrate.

13. The semiconductor package of claim 10 , wherein the distance between the first image sensor chip and the second image sensor chip is in a range between 30 μm and 50 μm.

14. The semiconductor package of claim 10 , wherein a vertical thickness of the connection substrate is less than a vertical thickness of the first image sensor chip.

15. A semiconductor package comprising:
a package substrate;
a connection substrate on the package substrate;
a first image sensor chip on the connection substrate;
a second image sensor chip horizontally spaced apart from the first image sensor chip on the connection substrate;
a plurality of lenses including first and second lenses vertically overlapping the first and second image sensor chips respectively;
a lens holder supporting the plurality of lenses;
a memory chip disposed on the package substrate and electrically connected to the first image sensor chip through the connection substrate; and
a logic chip disposed on the package substrate and horizontally spaced apart from the memory chip,
wherein the lens holder comprises sidewalls extending vertically from a top surface of the package substrate and an upper portion extending horizontally from the sidewalls and holding the plurality of lenses such that the lens holder and the plurality of lenses together with the package substrate enclose the first and second image sensor chips,
wherein the upper portion of the lens holder is disposed at the same height as the plurality of lenses,
wherein a portion of the lens holder is interposed between the plurality of lenses,
wherein the portion of the lens holder contacts the plurality of lenses, and
wherein a distance between the first image sensor chip and the second image sensor chip is less than a distance between the memory chip and the logic chip.

16. The semiconductor package of claim 15 , wherein the distance between the first image sensor chip and the second image sensor chip is less than a vertical thickness of the connection substrate.

17. The semiconductor package of claim 15 , wherein the distance between the first image sensor chip and the second image sensor chip is less than a vertical thickness of the first image sensor chip and a vertical thickness of the second image sensor chip.

18. The semiconductor package of claim 15 , wherein a ve

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Yonghoe
• Seo Sunkyoung
• Jo Chajea

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title