Hierarchical large block synthesis (HLBS) filling

Patent metadata

Field	Value
Publication number	US-11775730-B2
Application number	US-202117402806-A
Country	US
Kind code	B2
Filing date	Aug 16, 2021
Priority date	Aug 16, 2021
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

Aspects of the invention include a computer-implemented method of hierarchical large block synthesis (HLBS). At least a partial ring is created around an HLBS structure. The partial ring includes at least one or more of filler elements, which are engineering change order (ECO) books for adding repeaters to wire dominated nets, and decoupling capacitors of relatively large sizes. Certain areas of the HLBS structure within the partial ring that exhibit a unique characteristic are identified. Decoupling capacitors of the relatively large sizes are disposed in the certain areas. A remainder of the areas of the HLBS structure are filled with engineering change order (ECO) books and decoupling capacitors of relatively small sizes.

First claim

What is claimed is:

1. A computer-implemented method of hierarchical large block synthesis (HLBS), comprising:
creating at least a partial ring around an HLBS structure to comprise at least one or more filler elements, which are engineering change order (ECO) books for adding repeaters to wire dominated nets, and decoupling capacitors of relatively large sizes;
identifying certain areas of the HLBS structure within the partial ring that exhibit a unique characteristic;
disposing decoupling capacitors of the relatively large sizes in the certain areas; and
filling a remainder of the areas of the HLBS structure with engineering change order (ECO) books and decoupling capacitors of relatively small sizes.

2. The computer-implemented method according to claim 1 , wherein the creating of at least the partial ring comprises creating a full ring around the HLBS structure.

3. The computer-implemented method according to claim 1 , wherein the partial ring has an open section.

4. The computer-implemented method according to claim 1 , wherein the unique characteristic comprises a voltage (IR) sensitivity.

5. The computer-implemented method according to claim 1 , wherein the decoupling capacitors of the relatively large sizes are about 0.96 μm×0.648 μm or larger and the decoupling capacitors of the relatively small sizes are about 0.96 μm×0.324 μm.

6. The computer-implemented method according to claim 1 , wherein the disposing of the decoupling capacitors of the relatively large sizes in the certain areas comprises forming linear arrays of the decoupling capacitors of the relatively large sizes.

7. The computer-implemented method according to claim 6 , wherein the linear arrays extend from opposite sides of the partial ring.

8. A computer program product for hierarchical large block synthesis (HLBS), the computer program product comprising:
a memory; and
a processing system configured to perform a method comprising:
creating at least a partial ring around an HLBS structure to comprise at least one or more of filler elements, which are engineering change order (ECO) books for adding repeaters to wire dominated nets, and decoupling capacitors of relatively large sizes;
identifying certain areas of the HLBS structure within the partial ring that exhibit a unique characteristic;
disposing decoupling capacitors of the relatively large sizes in the certain areas; and
filling a remainder of the areas of the HLBS structure with engineering change order (ECO) books and decoupling capacitors of relatively small sizes.

9. The computer program product according to claim 8 , wherein the creating of at least the partial ring comprises creating a full ring around the HLBS structure.

10. The computer program product according to claim 8 , wherein the creating of at least the partial ring comprises creating one or more of a U-shape, an L-shape and a line at least partially around or along a section of the HLBS structure.

11. The computer program product according to claim 8 , wherein the unique characteristic comprises a voltage (IR) sensitivity.

12. The computer program product according to claim 8 , wherein the decoupling capacitors of the relatively large sizes are about 0.96 μm×0.648 μm or larger and the decoupling capacitors of the relatively small sizes are about 0.96 μm×0.324 μm.

13. The computer program product according to claim 8 , wherein the disposing of the decoupling capacitors of the relatively large sizes in the certain areas comprises forming linear arrays of the decoupling capacitors of the relatively large sizes.

14. The computer program product according to claim 13 , wherein the linear arrays extend from opposite sides of the partial ring.

15. A system for hierarchical large block synthesis (HLBS), comprising:
a memory having computer readable instructions; and
one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
creating at least a partial ring around an HLBS structure to comprise at least one or more of filler elements, which are engineering change order (ECO) books for adding repeaters to wire dominated nets, and decoupling capacitors of relatively large sizes;
identifying certain areas of the HLBS structure within the partial ring that exhibit a unique characteristic;
disposing decoupling capacitors of the relatively large sizes in the certain areas; and
filling a remainder of the areas of the HLBS structure with engineering change order (ECO) books and decoupling capacitors of relatively small sizes.

16. The system according to claim 15 , wherein the creating of at least the partial ring comprises creating a full ring around the HLBS structure.

17. The system according to claim 15 , wherein the creating of at least the partial ring comprises creating one or more of a U-shape, an L-shape and a line at least partially around or along a section of the HLBS structure.

18. The system according to claim 15 , wherein the unique characteristic comprises a voltage (IR) sensitivity.

19. The system according to claim 15 , wherein the decoupling capacitors of the relatively large sizes are about 0.96 μm×0.648 μm or larger and the decoupling capacitors of the relatively small sizes are about 0.96 μm×0.324 μm.

20. The system according to claim 15 , wherein the disposing of the decoupling capacitors of the relatively large sizes in the certain areas comprises forming linear arrays of the decoupling capacitors of the relatively large sizes that extend from opposite sides of the partial ring.

Assignees

• IBM

Inventors

• Geva Ofer
• Duffy Brittany
• Schell Timothy A
• Herkel Eduard
• Surprise Jesse Peter

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title