Accommodating engineering change orders in integrated circuit design

Patent metadata

Field	Value
Publication number	US-9953121-B2
Application number	US-201615144969-A
Country	US
Kind code	B2
Filing date	May 3, 2016
Priority date	May 3, 2016
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A computer-implemented method includes identifying an in initial register-transfer-level description for an integrated circuit design and adding one or more spare latches to the initial register-transfer-level description to yield a modified register-transfer-level description for the integrated circuit design. The computer-implemented method further includes performing placement and routing for the modified register-transfer-level description to yield a gate-level description for the integrated circuit design. The one or more spare latches exist in said gate-level description. The computer-implemented method further includes converting at least one of the one or more spare latches in the gate-level description into a reconfigurable latch filler cell to yield a modified gate-level description for the integrated circuit design and finalizing the integrated circuit design. A corresponding computer program product and computer system are also disclosed.

First claim

What is claimed is:

1. A computer-implemented method comprising:
identifying an initial register-transfer-level description for an integrated circuit design;
adding one or more spare latches to said initial register-transfer-level description to yield a modified register-transfer-level description for said integrated circuit design;
performing synthesis, placement, and routing for said modified register-transfer-level description to yield a gate-level description for said integrated circuit design, wherein said one or more spare latches exist in said gate-level description;
converting at least one of said one or more spare latches in said gate-level description into a reconfigurable latch filler cell to yield a modified gate-level description for said integrated circuit design; and
finalizing said integrated circuit design;

reading from a control file, said control file identifying a predetermined ratio for a quantity of said one or more spare latches to a number of operational latches for said integrated circuit design; and
calculating said quantity of said one or more spare latches, based on said predetermined ratio and said number of operational latches;

and, wherein:
adding one or more spare latches to said initial register-transfer-level description comprises adding said quantity of said one or more spare latches to said initial register-transfer-level description.

2. The computer-implemented method of claim 1 , wherein said reconfigurable latch filler cell comprises at least one disconnection from a power rail.

3. The computer-implemented method of claim 1 , wherein said reconfigurable latch filler cell comprises at least one disconnection from a clock pin.

4. The computer-implemented method of claim 1 , wherein:
at least one said reconfigurable latch filler comprises a scan input connection and a scan output connection; and
said scan input connection is shorted to said scan output connection in said gate-level description.

5. The computer-implemented method of claim 1 , wherein at least one said reconfigurable latch filler cell has an area footprint no larger than that of an operational latch of said integrated circuit design.

6. The computer-implemented method of claim 1 , further comprising:
identifying one or more clock buffers for said integrated circuit design;
determining an optimal clock buffer size for said one or more clock buffers, based on a quantity of said one or more spare latches; and
preventing one or more optimization routines from reducing said one or more clock buffers below said optimal clock buffer size.

7. A computer-implemented method, comprising:
receiving a register-transfer-level description and a gate-level description for an integrated circuit design, wherein said gate-level description comprises one or more spare latches implemented as reconfigurable latch filler cells;
receiving an engineering change order for said integrated circuit design, wherein said engineering change order requires at least one additional latch;
responsive to said engineering change order, adding said at least one additional latch to said register-transfer-level description;
for at least one of said at least one additional latch, selecting one of said one or more spare latches in said register-transfer-level description to yield a selected spare latch;
for said selected spare latch, identifying a selected reconfigurable latch filler cell in said gate-level description;
replacing said selected reconfigurable latch filler cell with an operational latch in said gate-level description; and
finalizing said integrated circuit design;
wherein said operational latch is identical in area footprint to and pin-compatible with an originally designed latch.

8. The computer-implemented method of claim 7 , wherein:
at least one said reconfigurable latch filler comprises a scan input connection connected to a scan output connection by a short; and
replacing said selected reconfigurable latch filler cell with an operational latch in said gate-level description comprises removing said short.

9. The computer-implemented method of claim 7 , wherein:
said reconfigurable latch filler cell comprises at least one disconnection from a power rail; and
replacing said selected reconfigurable latch filler cell with an operational latch in said gate-level description comprises connecting said reconfigurable latch filler cell to said power rail.

10. The computer-implemented method of claim 7 , wherein:
said reconfigurable latch filler cell comprises at least one disconnection from a clock pin; and
replacing said selected reconfigurable latch filler cell with an operational latch in said gate-level description comprises connecting said reconfigurable latch filler cell to said clock pin.

11. The computer-implemented method of claim 7 , further comprising:
generating a netlist from said gate-level description;
routing said engineering change order based on said netlist; and
omitting re-ordering a scan chain for said integrated circuit design.

12. The computer-implemented method of claim 7 , further comprising:
identifying one or more clock buffers for said integrated circuit design, said one or more clock buffers having been sized for said one or more spare latches; and
reducing said one or more clock buffers to an optimized clock buffer size, based on a number of instantiated latches in said integrated circuit design.

13. A method of producing an integrated circuit comprising:
producing an integrated circuit design;
adding at least one spare latch design to said integrated circuit design;
replacing at least one of said at least one spare latch design with a reconfigurable latch filler cell design;
manufacturing a first collection of masks for said integrated circuit design;
responsive to a metal-only engineering change order, manufacturing a second collection of masks for said integrated circuit design; and
manufacturing an integrated circuit from said integrated circuit design using said second collection of masks and at least one mask from said first collection of masks;

and, wherein:
said second collection of masks implements said metal-only engineering change order;
said second collection of masks define converting at least one said reconfigurable latch filler cell into an operational latch;
said first collection of masks comprises only masks for processes unaffected by metal-only engineering change order; and
said first collection of masks define at least one said reconfigurable latch filler cell design.

14. The method of producing an integrated circuit of claim 13 , further comprising:
converting at least one said reconfigurable latch filler cell design to an operational latch design by a metal-only engineering change order.

Assignees

• IBM

Inventors

• Datta Ayan
• Gupta Saurabh
• Udhayakumar Jayaprakash
• Veerabhadraiah Rajesh
• Verma Alok

Classifications

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F2119/08

  Thermal analysis or thermal optimisation · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title