Method and system for generating layout diagram for semiconductor device having engineering change order (ECO) cells

Patent metadata

Field	Value
Publication number	US-10970440-B2
Application number	US-202016895803-A
Country	US
Kind code	B2
Filing date	Jun 8, 2020
Priority date	Sep 30, 2016
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

A method of manufacturing a semiconductor device (for a layout diagram stored on a non-transitory computer-readable medium) includes generating the layout diagram. The generating the layout diagram includes: placing standard functional cells to partially fill a logic area of the layout diagram according to at least one corresponding schematic design thereby leaving, as unfilled, a spare region in the logic area; selecting a first pitch for additional cells to be placed in the spare region, wherein use of the first pitch minimizes wasted space in the spare region; selecting standard not-yet-programmed (SNYP) spare cells, which are to become at least some of the additional cells, according to the first pitch; and placing the selected SNYP spare cells into the spare region of the layout diagram.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, for a layout diagram stored on a non-transitory computer-readable medium, the method comprising generating the layout diagram including:
placing standard functional cells to partially fill a logic area of the layout diagram according to at least one corresponding schematic design thereby leaving, as unfilled, a spare region in the logic area;
selecting a first pitch for additional cells to be placed in the spare region, wherein use of the first pitch minimizes wasted space in the spare region;
selecting standard not-yet-programmed (SNYP) spare cells, which are to become at least some of the additional cells, according to the first pitch; and
placing the selected SNYP spare cells into the spare region of the layout diagram.

2. The method of claim 1 , further comprising:
performing at least one of the following including:
making one or more lithographic exposures based on the layout diagram;
fabricating, based on the layout diagram, one or more semiconductor masks; or
fabricating, based on the layout diagram, at least one component in a layer of a semiconductor integrated circuit.

3. The method of claim 1 , wherein the selecting a first pitch includes:
choosing the first pitch based on a second pitch of strap lines of a metallization layer in the layout diagram.

4. The method of claim 3 , wherein the choosing the first pitch based on a second pitch includes:
generating a set of possible values for the first pitch based on the second pitch; and
selecting one member of the set of possible values to be the first pitch.

5. The method of claim 4 , wherein the generating the set of possible values for the first pitch includes:
calculating a first group of first candidate integers, each first candidate positive integer being positive and evenly divisible into the second pitch;
calculating a second group of second candidate positive integers, each second candidate positive integer being positive evenly divisible by a number of masks selected to produce the metallization layer; and
intersecting the first and second groups to form a third group of candidate integers; and
the third group represents the set of possible values for the first pitch.

6. The method of claim 4 , wherein the selecting one member of the set of possible values includes:
choosing a smallest member of the set of possible values to be the first pitch, where the first pitch is represented by first_pitch, such that
2<first_pitch.

7. The method of claim 3 , wherein:
the first pitch is smaller than the second pitch.

8. The method of claim 3 , wherein:
the metallization layer is a first metallization layer M1.

9. The method of claim 1 , wherein:
the first pitch extends in a first direction; and
the method further comprises:
reserving, in each SNYP spare cell, a reserved-portion over which one or more strap lines are formable, each reserved-portion extending in a second direction across the SNYP spare cell, the second direction being substantially perpendicular to the first direction; and
locating each reserved-portion such that a remaining portion of the SNYP spare cell is undivided.

10. A method of manufacturing a semiconductor device, for a layout diagram stored on a non-transitory computer-readable medium, the method comprising generating the layout diagram including:
placing standard functional cells to partially fill a logic area of the layout diagram according to at least one corresponding schematic design thereby leaving, as unfilled, a spare region in the logic area;
selecting a first pitch for additional cells to be placed in the spare region based on a second pitch of strap lines of a metallization layer in the layout diagram, wherein use of the first pitch minimizes wasted space in the spare region;
selecting standard not-yet-programmed (SNYP) spare cells, which are to become at least some of the additional cells, according to the first pitch; and
placing the selected SNYP spare cells into the spare region of the layout diagram.

11. The method of claim 10 , further comprising:
performing at least one of the following including:
making one or more lithographic exposures based on the layout diagram;
fabricating, based on the layout diagram, one or more semiconductor masks; or
fabricating, based on the layout diagram, at least one component in a layer of a semiconductor integrated circuit.

12. The method of claim 10 , wherein the selecting a first pitch includes:
generating a set of possible values for the first pitch based on the second pitch; and
selecting one member of the set of possible values to be the first pitch; and
wherein:
the generating a set of possible values including:
receiving a value representing a number, CLR, of masks selected to produce the metallization layer; and
calculating a set Δ of candidate integers δ, Δ={δ}, each candidate δ being positive and evenly divisible into the first pitch and each candidate δ matching an even/odd status of the value representing the number CLR of masks such that:

{
δ
}

=

(

0
=

first_strap
⁢
mod

⁢

⁢
δ

AND

0
=

δ
⁢

⁢
mod
⁢

⁢
CLR

)

;

  and
the selecting one member of the set of possible values includes;
selecting one member from the set Δ ={δ} to be the second pitch.

13. The method of claim 12 , wherein the selecting one member from the set Δ ={δ} includes:
choosing a smallest member of the set Δ={δ} to be the second pitch such that
second_pitch=min{δ}.

14. The method of claim 10 , wherein the selecting a first pitch includes:
generating a set of possible values for the first pitch based on the second pitch; and
selecting one member of the set of possible values to be the first pitch; and
wherein:
the generating the set of possible values for the first pitch includes:
calculating a first group of first candidate positive integers, each first candidate integer bein

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiu Mao-Wei
• Chiang Ting-Wei
• Zhuang hui-zhong
• Tien Li-Chun
• Lu Chi-Yu

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title