Memory lookup computing mechanisms

Patent metadata

Field	Value
Publication number	US-11775294-B2
Application number	US-202117538556-A
Country	US
Kind code	B2
Filing date	Nov 30, 2021
Priority date	Dec 26, 2017
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.

First claim

What is claimed is:

1. A method comprising:
performing, by a memory device, a first operation by retrieving a result of the first operation from a lookup table (LUT) stored on the memory device;
sending, by the memory device, the result of the first operation to a logic device; and
performing, by the logic device, a second operation using the result of the first operation performed on the memory device.

2. The method of claim 1 , wherein the memory device stores whole product multiplication results and the first operation comprises:
retrieving, by the memory device, a whole scalar multiplication result stored on the memory device using a whole scalar floating point input;
sending, by the memory device, the whole scalar multiplication result stored on the memory device to a buffer on the logic device;
sending, by the buffer, the whole scalar multiplication result to an accumulator on the logic device; and
accumulating, by the accumulator, the whole scalar multiplication result.

3. The method of claim 1 , wherein the memory device stores partial product multiplication results and the first operation comprises:
using, by the memory device, a fraction scalar floating point input to retrieve a partial product multiplication result stored on the memory device;
sending, by the memory device, the partial product multiplication result to a buffer on the logic device;
sending, by the buffer, the partial product multiplication result to an adjustor on the logic device;
sending, by the adjustor, the partial product multiplication result to an accumulator on the logic device; and
accumulating, by the accumulator, the partial product multiplication result.

4. The method of claim 1 , wherein the memory device stores tensor multiplication results and the first operation comprises:
retrieving, by the memory device, a tensor multiplication result stored on the memory device using a tensor floating point input;
sending, by the memory device, the tensor multiplication result to a buffer on the logic device; and
sending, by the buffer, the tensor multiplication result to a tensor post-processor on the logic device.

5. The method of claim 1 , wherein the memory device stores whole product multiplication results and the first operation comprises:
retrieving, by the memory device, a whole scalar multiplication result stored on the memory device using a whole scalar floating point;
sending, by the memory device, the whole product multiplication results to a buffer device comprising a plurality of buffers;
sending, by the buffer device, the whole product multiplication result to a buffer of the logic device; and
sending, by the buffer of the logic device, the whole product multiplication result to a tensor processor on the logic device.

6. The method of claim 1 , further comprising:
reading every possible location in a first layer input feature map;
convolving with the first layer input feature map with a first layer kernel; and
generating results of a second layer input feature map based on the convolving.

7. A memory lookup mechanism comprising: a logic device; and a memory device, wherein the memory device performs operations comprising:
performing a first operation by retrieving a result of the first operation from a lookup table (LUT) stored on the memory device; and
sending the result of the first operation to the logic device for use by the logic device to perform a second operation.

8. The memory lookup mechanism of claim 7 , wherein the memory device stores whole product multiplication results and the memory device performs operations further comprising:
retrieving a whole scalar multiplication result stored on the memory device using a whole scalar floating point input; and
sending the whole scalar multiplication result stored on the memory device to a buffer on the logic device.

9. The memory lookup mechanism of claim 8 , wherein the logic device further comprises an accumulator, the accumulator performing operations comprising:
receiving the whole scalar multiplication result from the buffer; and
accumulating the whole scalar multiplication result.

10. The memory lookup mechanism of claim 7 , wherein the memory device stores partial product multiplication and the memory device performs operations further comprising:
retrieving a partial product multiplication result stored on the memory device using a fraction scalar floating point input; and
sending the partial product multiplication result to a buffer on the logic device.

11. The memory lookup mechanism of claim 10 , wherein the logic device further comprises:
an adjustor, the adjustor receiving the partial product multiplication result from the buffer; and
an accumulator, the accumulator performing operations comprising:
receiving the partial product multiplication result from the adjustor; and
accumulating the partial product multiplication result.

12. The memory lookup mechanism of claim 7 , wherein the memory device stores tensor multiplication results and the memory device performs operations further comprising:
retrieving a tensor multiplication result stored on the memory device using a tensor floating point input; and
sending the tensor multiplication result to a buffer on the logic device.

13. The memory lookup mechanism of claim 12 , wherein the logic device further comprises a tensor post-processor receiving the tensor multiplication result from the buffer.

14. The memory lookup mechanism of claim 7 , wherein the memory device stores whole product multiplication results and the memory device performs operations further comprising:
retrieving a whole scalar multiplication result stored on the memory device using a whole scalar floating point; and
sending the whole product multiplication results to a buffer.

15. The memory lookup mechanism of claim 14 , wherein the logic device further comprises a tensor processor, the tensor processor receiving the whole product multiplication results from the buffer.

16. The memory lookup mechanism of claim 7 , wherein the logic device further comprises an accelerator.

17. The memory lookup mechanism of claim 7 , wherein the memory device comprises a dynamic random access memory (DRAM) device.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Gu Peng
• Malladi Krishna T
• Zheng Hongzhong

Classifications

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F7/00

  Methods or arrangements for processing data by operating upon the order or content of the data handled (logic circuits H03K19/00) · CPC title

• G06F7/4876 Primary

  Multiplying · CPC title

• G06F9/3004 Primary

  to perform operations on memory · CPC title

• G06F12/0207

  with multidimensional access, e.g. row/column, matrix · CPC title