Space-multiplexing DRAM-based reconfigurable logic

Patent metadata

Field	Value
Publication number	US-9503095-B2
Application number	US-201514838348-A
Country	US
Kind code	B2
Filing date	Aug 27, 2015
Priority date	Dec 16, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

According to one general aspect, an apparatus may include a random access memory array that, in turn, includes a reconfigurable look-up table. The reconfigurable look-up table may include memory cells configured to simultaneously store a plurality of look-up tables, wherein each look-up table is associated with a respective logic function. The reconfigurable look-up table may include a local row decoder configured to activate one or more rows of memory cells based upon a set of input signals. The reconfigurable look-up table may be configured to perform one logic function at a time, and wherein the logic function is dynamically selected. The plurality of look up tables stored in the memory cells may be configured to be dynamically altered via a write operation to the random access memory array.

First claim

What is claimed is:

1. An apparatus comprising:
a random access memory array comprising a reconfigurable look-up table, wherein the reconfigurable look-up table comprises:
memory cells configured to simultaneously store a plurality of look-up tables, wherein each look-up table is associated with a respective logic function, and
a local row decoder configured to activate one or more rows of memory cells based upon a set of input signals;

wherein the reconfigurable look-up table is configured to execute one or more dynamically selected logic function at a time; and
wherein the plurality of look up tables stored in the memory cells is configured to be dynamically altered via a write operation to the random access memory array.

2. The apparatus of claim 1 , wherein a subset of the set of input signals is active based upon which logic function is selected.

3. The apparatus of claim 1 , wherein the reconfigurable look-up table includes an input decoder configured to route the one or more of set of inputs to the local row decoder based upon which logic function is selected.

4. The apparatus of claim 1 , wherein the reconfigurable look-up table includes an internal clock signal and an external clock signal; and
wherein a number of the plurality of look-up tables stored by the memory cells is associated with the ratio of a frequency of the internal clock signal to a frequency of the external clock signal.

5. The apparatus of claim 1 , wherein the reconfigurable look-up table is configured to time-division multiplex between the plurality of look-up tables.

6. The apparatus of claim 1 , wherein the random access memory array comprises at least two reconfigurable look-up tables, each reconfigurable look-up table storing respective one or more look-up tables, wherein each look-up table is associated with a respective logic function;
wherein the at least two reconfigurable look-up tables are electrically coupled such that an output of one of the two reconfigurable look-up tables is the input to the other reconfigurable look-up table; and
wherein the at least two reconfigurable look-up tables are configured to cycle through their respective logic functions in order to perform a pipelined logic operation.

7. The apparatus of claim 1 , wherein the reconfigurable look-up table comprises an output selector configured to select between a plurality of sets of output signals based upon a selected logic function; and
wherein each set of output signals is associated with a respective one of the look-up tables.

8. The apparatus of claim 1 , wherein the reconfigurable look-up table includes a first minimum number of input signals, and a first minimum number of output signals;
wherein each logic function includes a second minimum number of input signals, and a second minimum number of output signals;
wherein the second minimum number of input signals is less than or equal to the first minimum number of input signals; and
wherein the second minimum number of output signals is less than or equal to the first minimum number of output signals.

9. The apparatus of claim 1 , wherein the reconfigurable look-up table includes a logic function selector configured to:
automatically select one of the respective logic functions to perform,
based upon a selected logic function, select a set of input signals to be employed by the local row decoder,
based upon the selected logic function, select a set out output signals to be output by the reconfigurable look-up table.

10. A system-on-a-chip comprising:
a random access memory array comprising a reconfigurable look-up table, wherein the reconfigurable look-up table comprises:
memory cells configured to simultaneously store a plurality of look-up tables, wherein each look-up table is associated with a respective logic function, and
a logic function selector configured to dynamically select one the of plurality of look-up tables to be active;

wherein the reconfigurable look-up table is configured to perform the selected logic function; and
a processor configured to off-load an execution of at least the selected logic function to the reconfigurable look-up table.

11. The system-on-a-chip of claim 10 , wherein the processor is configured to off-load an execution of a series of logic functions to the reconfigurable look-up table, wherein each of the series of logic functions is associated with a look-up table stored by the reconfigurable look-up table; and
wherein the reconfigurable look-up table is configured to dynamically switch a selection of an active logic function to execute each of the series of logic functions in turn.

12. The system-on-a-chip of claim 10 , wherein the processor is configured to off-load an execution a plurality of logic functions to the reconfigurable look-up table, wherein each of the plurality of logic functions is associated with a look-up table stored by the reconfigurable look-up table; and
wherein the reconfigurable look-up table includes:
an internal clock signal that operates at a multiple of an external clock signal, and
wherein the reconfigurable look-up table is configured to, according to the internal clock signal, dynamically select and execute the plurality of logic functions within a period of the external clock signal.

13. The system-on-a-chip of claim 10 , wherein the processor is configured to off-load an execution of a plurality of logic functions to the reconfigurable look-up table, wherein each of the plurality of logic functions is associated with a look-up table stored by the reconfigurable look-up table; and
wherein the reconfigurable look-up table is configured to execute at least two of the plurality of logic functions per clock cycle by multiplexing.

14. The system-on-a-chip of claim 10 , wherein the reconfigurable look-up table is configured to time-division multiplex between the plurality of look-up tables.

15. The system-on-a-chip of claim 10 , wherein the random access memory array comprises at least a first reconfigurable look-up table and a second reconfigurable look-up table, each reconfigurable look-up table storing respective one or more of look-up tables, wherein each look-up table is associated with a respective logic function;
wherein the at least two reconfigurable look-up tables are electrically coupled such that an output of the first reconfigurable look-up table is an input to the second reconfigurable look-up table; and
wherein the first reconfigurable look-up table and the second reconfigurable look-up table are configured to cycle through their respective logic functions in order to perform a pipelined logic operation.

16. The system-on-a-chip of claim 10 , wherein the reconfigurable look-up table includes a logic function selector configured to:
automatically select one of the respective logic functions to perform,
based upon a selected logic function, select a set of input signals to be employed by a local row decoder,
based upon the selected logic function, select a set out output signals to be output by the reconfigurable look-up table.

17. The system-on-a-chip of claim 10 , wherein the processor is configured to off-load an execution or at least the selected logic function to the reconfigurable look-up table by performing a write operation to the memory array; and
wherein the processor is configured to receive a result of the at least the selected logic function from the reconfigurable look-up table by performing a read operation to the memory array.

18. A method comprising:
storing a plurality of look-up tables in a sub-array of

Assignees

• Samsung Electronics Co Ltd

Inventors

• Gao Mingyu
• Zheng Hongzhong
• Malladi Krishna T

Classifications

• H10W90/00

  Package configurations · CPC title

• H03K19/17758

  for speeding up configuration or reconfiguration · CPC title

• H03K19/17736

  Structural details of routing resources · CPC title

• H03K19/1776 Primary

  for memories · CPC title

• H03K19/17728

  Reconfigurable logic blocks, e.g. lookup tables · CPC title