Method for changing an integrated circuit design

Patent metadata

Field	Value
Publication number	US-11769764-B2
Application number	US-202016918289-A
Country	US
Kind code	B2
Filing date	Jul 1, 2020
Priority date	Jul 19, 2019
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

Disclosed is a method for designing an integrated circuit, wherein the integrated circuit is to be structured in cells, wherein the cells are to comprise functional cells and spare cells. The method comprises: a) designing at least one functional cell; and b) placing a plurality of functional cells on associated pattern positions of an, in particular regular, pattern matrix designed for the functional cells. The method further comprises c) placing, on at least one of the remaining pattern positions of the pattern matrix and instead of at least one spare cell conceivable for the at least one of the remaining pattern positions of the pattern matrix, a gate-based decoupling cell, and alternatively or in addition, d) placing, in at least one gap between pattern positions of the matrix pattern and instead of at least one filler cell conceivable for the at least one gap between pattern positions of the pattern matrix, a gate-based decoupling cell.

First claim

The invention claimed is:

1. A method for changing an integrated circuit design, the method comprising:
providing at least one functional cell for the integrated circuit design;
replacing a spare cell for the integrated circuit design with a gate-based decoupling cell, wherein the gate-based decoupling cell includes an n-type diffusion region, a p-type diffusion region, and a plurality of polysilicon lines, each polysilicon line of the plurality of polysilicon lines extending over both the n-type diffusion region and the p-type diffusion region, the n-type and p-type diffusion regions both connected to a first power supply line and the plurality of polysilicon lines connected to a second power supply line, wherein the first power supply line is for receiving a power supply voltage that is different from a power supply voltage received by the second power supply line; and
reconfiguring the the gate-based decoupling cell for the integrated circuit design to a logic function in response to an engineering change order (ECO), wherein the gate-based decoupling cell is reconfigured by removing the second power supply line connections to the polysilicon lines and the first power supply line connections to the n-type and p-type diffusion layers, and adding new connections to implement the logic function.

2. The method according to claim 1 , wherein the first and second power supply lines are formed in one or more metal layers and reconfiguring the gate-based decoupling cell further comprises removing the one or more metal layers and adding one or more new metal layers.

3. The method according to claim 1 , wherein a first power supply voltage received by the first power supply line is at ground potential, and a second power supply voltage received by the second power supply line is a positive power supply voltage.

4. The method according to claim 1 , further comprising verifying all design-wise and process-wise requirements of the changed integrated circuit design, including that of the at least one functional cells and the cell.

5. The method according to claim 1 ,
wherein the reconfiguring of the gate-based decoupling cell is performed manually by an integrated circuit design engineer, or
wherein the reconfiguring of the gate-based decoupling cell comprises selecting a design for the logic function from a library.

6. A method for changing an integrated circuit design, the method comprising:
providing a plurality of functional cells for the integrated circuit design;
replacing a plurality of spare cells for the integrated circuit design with a plurality of gate-based decoupling cells, wherein each of the gate-based decoupling cells includes an n-type diffusion region, a p-type diffusion region, and a plurality of poly silicon lines, each poly silicon line of the plurality of poly silicon lines extending over both the n-type diffusion region and the p-type diffusion region, the n-type and p-type diffusion regions both connected to a first power supply line and the plurality of polysilicon lines connected to a second power supply line, wherein the first power supply line is for receiving a power supply voltage that is different from a power supply voltage received by the second power supply line; and
reconfiguring the gate-based decoupling cells for the integrated circuit design to a logic function in response to an engineering change order (ECO), wherein each of the gate-based decoupling cells is reconfigured by removing the second power supply line connections to the polysilicon lines and the first power supply line connections to the n-type and p-type diffusion layers, and adding new connections to implement the logic function.

7. The method according to claim 6 , wherein the first and second power supply lines are formed in one or more metal layers and reconfiguring the gate-based decoupling cells further comprises removing the one or more metal layers and adding one or more new metal layers.

8. The method according to claim 6 , wherein a first power supply voltage received by the first power supply line is at ground potential, and a second power supply voltage received by the second power supply line is a positive power supply voltage.

Assignees

• Nxp Bv

Inventors

• Trester Sven

Classifications

• H10D84/0172

  Manufacturing their gate conductors · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D1/66

  Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors · CPC title

• H10D84/942

  Resistors and capacitors · CPC title