Semiconductor device having engineering change order (ECO) cells and method of using

Patent metadata

Field	Value
Publication number	US-10553575-B2
Application number	US-201715815289-A
Country	US
Kind code	B2
Filing date	Nov 16, 2017
Priority date	Aug 13, 2013
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

A semiconductor device includes an array of Engineering Change Order (ECO) cells. Each of the ECO cells in the array includes a first metal pattern and a second metal pattern. Each of the ECO cells in the array further includes a plurality of active area patterns isolated from each other and arranged between the first and second metal patterns. Each of the ECO cells in the array further includes a first central metal pattern overlapping the first metal pattern. Each of the ECO cells in the array further includes a via electrically connecting the first central metal pattern to the first metal pattern. The plurality of active area patterns is arranged symmetrically about the first central metal pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising an array of Engineering Change Order (ECO) cells, each of the ECO cells in the array comprising:
a first metal pattern;
a second metal pattern;
a plurality of active area patterns isolated from each other and arranged between the first and second metal patterns, wherein the plurality of active area patterns is spaced from the first metal pattern and the second metal pattern in a plan view; and
a first central metal pattern overlapping the first metal pattern; and
a via electrically connecting the first central metal pattern to the first metal pattern,
wherein the plurality of active area patterns is arranged symmetrically about the first central metal pattern
for each of the plurality of active area patterns in each of the ECO cells,
at least one polysilicon pattern overlapping a first active area pattern of the plurality of active area patterns; and
two additional metal patterns overlapping the first active area pattern and arranged on opposite sides of the corresponding at least one polysilicon pattern,
wherein
the additional metal patterns and the first and second central metal patterns belong to a first metal layer, and
the first and second metal patterns belong to a second metal layer above the first metal layer.

2. The semiconductor device of claim 1 , further comprising, for each of the ECO cells,
a second central metal pattern aligned with the first central metal pattern and overlapping the second metal pattern, wherein the plurality of active area patterns is arranged symmetrically about the second central metal pattern.

3. The semiconductor device of claim 2 , further comprising, for each of the ECO cells,
a second via electrically connecting the second central metal pattern with the second metal pattern.

4. The semiconductor device of claim 1 , wherein at least one of the ECO cells is in an unprogrammed state in which the polysilicon patterns and the two additional metal patterns are electrically isolated from the first and second metal patterns and from the first central metal pattern.

5. The semiconductor device of claim 1 , wherein at least one of the ECO cells is in a programmed state in which at least one of the polysilicon patterns or at least one of the two additional metal patterns is electrically connected with at least one of the first metal pattern or the second metal patterns and the first central metal pattern.

6. A method, comprising:
designing or manufacturing a semiconductor device, the semiconductor device comprising:
a functional circuit, and

an Engineering Change Order (ECO) cell in an unprogrammed state, the ECO cell comprising a plurality of transistors arranged symmetrically about a symmetrical axis, and first and second central metal patterns along the symmetrical axis, the first and second central metal patterns overlapping and electrically connected with a power line and a ground line, respectively, at least one polysilicon pattern overlapping a first active area pattern, two additional metal patterns overlapping the first active area pattern and arranged on opposite sides of the corresponding at least one polysilicon pattern, wherein the additional metal patterns and the first and second central metal patterns belong to a first metal layer, and the first and second central metal patterns belong to a second metal layer above the first metal layer;
testing the functional circuit;
programming, based on a result of the testing, the ECO cell; and
routing the programmed ECO cell to the functional circuit.

7. The method of claim 6 , wherein the programming comprises
modifying, in the semiconductor device, only a metal layer immediately above and electrically connected with a lowermost via layer above the transistors.

8. The method of claim 6 , wherein the programming comprises
modifying, in the semiconductor device, only a lowermost via layer above the transistors and a metal layer immediately above and electrically connected with the lowermost via layer.

9. The method of claim 6 , wherein the programming comprises
modifying, in the semiconductor device, only a lowermost via layer above the transistors, a metal layer immediately above and electrically connected with the lowermost via layer, and a metal-over-polysilicon layer immediately above and electrically connected with gates of the transistors.

10. A method, comprising:
manufacturing a semiconductor device, the semiconductor device comprising:
a functional circuit, and
a plurality of Engineering Change Order (ECO) cells electrically separated from the functional circuit, wherein each ECO cell of the plurality of ECO cells comprises:
a plurality of transistors arranged symmetrically about a symmetrical axis,
a first central metal pattern along the symmetrical axis, wherein the first central metal pattern is electrically connected to a power line, and
a second central metal pattern along the symmetrical axis, wherein the second central metal pattern is electrically connected to a ground line;
at least one polysilicon pattern overlapping a first active area pattern; and
two additional metal patterns overlapping the first active area pattern and arranged on opposite sides of the corresponding at least one polysilicon pattern,

wherein
the additional metal patterns and the first and second central metal patterns belong to a first metal layer, and
the first and second central metal patterns belong to a second metal layer above the first metal layer

testing the functional circuit; and
electrically connecting at least one ECO cell of the plurality of ECO cells to the functional circuit based on results of the testing.

11. The method of claim 10 , wherein the electrically connecting of the at least one ECO cell to the functional circuit comprises modifying a via layer closest to the plurality of transistors, a metal layer immediately above the via layer, and a metal-over-polysilicon layer immediately above the plurality of transistors.

12. The method of claim 10 , wherein the electrically connecting the at least one ECO cell to the functional circuit comprises replacing a faulty portion of the functional circuit with the at least one ECO cell.

13. The method of claim 10 , wherein the electrically connecting the at least one ECO cell to the functional circuit comprises modifying functional of a portion of the functional circuit using the at least one ECO cell.

14. The method of claim 10 , wherein the electrically connecting the at least one ECO cell to the functional circuit comprises adding a new functionality to the functional circuit using the at least one ECO cell.

15. The method of claim 10 , wherein the electrically connecting the at least one ECO cell to the functional circuit comprises electrically connecting multiple ECO cells of the plurality of ECO cells to the functional circuit.

16. The method of claim 10 , further comprising retesting the functional circuit following the electrically connecting the at least one ECO cell to the functional circuit.

17. The method of claim 16 , further comprising electrically connecting a second ECO cell of the plurality of ECO cells to the functional circuit in response to results of the retesting of the functional circuit.

18. The method of claim 10 , wherein the electrically connecting the at least one ECO cell to the functional circuit comprises electrically connecting the at least one of the first central metal pattern or the second central metal pattern to a conductive pattern within the at least one ECO cell.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tien Li-Chun
• Chou Ya-Chi
• Zhuang hui-zhong
• Chen Chun-Fu
• Chiang Ting-Wei
• Tseng Hsiang Jen

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H01L27/11807

  Electricity · mapped topic

• H01L2027/11875

  Electricity · mapped topic

• G06F17/5068

  Physics · mapped topic

• H01L27/0207 Primary

  Electricity · mapped topic