Thermally-optimized tunable stack in cavity package-on-package

Patent metadata

Field	Value
Publication number	US-11769753-B2
Application number	US-201816051065-A
Country	US
Kind code	B2
Filing date	Jul 31, 2018
Priority date	Jul 31, 2018
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.

First claim

What is claimed is:

1. An electronics package, comprising:
a package substrate;
a first die coupled to the package substrate, the first die having a bottommost surface above an uppermost surface of an entirety of the package substrate;
a second die over the first die, wherein the first die and the second die are electrically coupled to the package substrate with wire bonds;
a cavity through the package substrate, wherein the cavity is within a footprint of the first die; and
a thermal stack in the cavity, wherein the thermal stack directly physically contacts the first die, and wherein the thermal stack is within the footprint of the first die.

2. The electronics package of claim 1 , wherein the thermal stack comprises a thermal interface material (TIM).

3. The electronics package of claim 1 , wherein the thermal stack comprises a substrate.

4. The electronics package of claim 3 , wherein the substrate comprises copper.

5. The electronics package of claim 3 , wherein the substrate comprises silicon.

6. The electronics package of claim 3 , wherein the thermal stack further comprises a TIM between the substrate and the first die.

7. The electronics package of claim 1 , wherein a width of the cavity is less than a width of the first die.

8. The electronics package of claim 1 , further comprising a mold layer over the first die and the package substrate.

9. The electronics package of claim 8 , wherein the thermal stack contacts a portion of the mold layer and the first die.

10. The electronics package of claim 1 , wherein the first die and the second die are memory dies.

11. The electronics package of claim 10 , wherein the first die and the second die are dynamic random access memory (DRAM) memory dies.

Assignees

• Intel Corp

Inventors

• Vakanas George
• Uppal Aastha
• Elhalawaty Shereen
• Mccann Aaron
• Cetegen Edvin
• Harirchian Tannaz
• Jayaraman Saikumar

Classifications

• H10W72/50

  Bond wires · CPC title

• H10W40/258

  Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title

• H10W40/22

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title