Apparatus and method for memory management in a graphics processing environment

Patent metadata

Field	Value
Publication number	US-11768781-B2
Application number	US-202217827556-A
Country	US
Kind code	B2
Filing date	May 27, 2022
Priority date	Apr 7, 2017
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

First claim

What is claimed is:

1. A graphics processor, comprising:
a plurality of graphics processing resources to execute instructions and process data;
partitioning hardware logic to indicate partitioning of the plurality of graphics processing resources into a plurality of slices, each slice of the plurality of slices including a corresponding subset of the graphics processing resources to be allocated to a corresponding virtual machine (VM);
a plurality of memory management circuits, each memory management circuit corresponding to a slice of the plurality of slices and configured to perform memory access operations including address translations, page fault operations, and page walk operations, each memory management circuit comprising:
one or more translation lookaside buffers (TLBs), each TLB to store at least some mappings of guest virtual addresses (GVAs) to host physical addresses (HPAs) maintained in page tables in a system memory, wherein each GVA is associated with a particular VM; and
an interface to couple the memory management circuit to a system-level memory management circuit, the interface to provide communication with the system-level memory management circuit to ensure coherency between mappings of GVAs to HPAs stored in the one or more TLBs and mappings of GVAs to HPAs stored in at least one TLB of the system-level memory management circuit.

2. The graphics processor of claim 1 wherein one or more slices are to be included in a first virtual graphics processing unit (vGPU) to be provided to a first VM, the first VM to execute one or more threads of a plurality of threads on the first vGPU.

3. The graphics processor of claim 2 wherein the first vGPU is uniquely identified with a first process address space identifier (PASID) value, and at least a second vGPU is uniquely identified with a second PASID value.

4. The graphics processor of claim 3 wherein the first PASID value is to be used by the address translation hardware logic to identify first page table entries and/or TLB entries associated with the first vGPU and the second PASID value is to be used by the address translation hardware logic to identify second page table entries and/or TLB entries associated with the second vGPU.

5. The graphics processor of claim 4 wherein the system memory comprises dynamic random access memory (DRAM).

6. The graphics processor of claim 5 wherein the DRAM comprises a high bandwidth memory (HBM).

7. The graphics processor of claim 1 wherein a first portion of the HPAs are to identify regions of a system memory and a second portion of the HPAs are to identify regions of a graphics processor memory.

8. The graphics processor of claim 7 wherein the graphics processor memory comprises a high bandwidth memory (HBM) and the system memory comprises a dynamic random access memory (DRAM) or an HBM.

9. A system, comprising:
a host processor;
a first memory interface to couple the host processor to a system memory;
a plurality of graphics processing resources to execute instructions and process data;
partitioning hardware logic to indicate partitioning of the plurality of graphics processing resources into a plurality of slices, each slice of the plurality of slices including a corresponding subset of the graphics processing resources to be allocated to a corresponding virtual machine (VM);
a plurality of memory management circuits, each memory management circuit corresponding to a slice of the plurality of slices and configured to perform memory access operations including address translations, page fault operations, and page walk operations, each memory management circuit comprising:
one or more translation lookaside buffers (TLBs), each TLB to store at least some mappings of guest virtual addresses (GVAs) to host physical addresses (HPAs) maintained in page tables in the system memory, wherein each GVA is associated with a particular VM; and
an interface to couple the memory management circuit to a system-level memory management circuit, the interface to provide communication with the system-level memory management circuit to ensure coherency between mappings of GVAs to HPAs stored in the one or more TLBs and mappings of GVAs to HPAs stored in at least one TLB of the system-level memory management circuit.

10. The system of claim 9 wherein one or more slices are to be included in a first virtual graphics processing unit (vGPU) to be provided to a first VM, the first VM to execute one or more threads of a plurality of threads on the first vGPU.

11. The system of claim 10 wherein the first vGPU is uniquely identified with a first process address space identifier (PASID) value, and at least a second vGPU is uniquely identified with a second PASID value.

12. The system of claim 11 wherein the first PASID value is to be used by the address translation hardware logic to identify first page table entries and/or TLB entries associated with the first vGPU and the second PASID value is to be used by the address translation hardware logic to identify second page table entries and/or TLB entries associated with the second vGPU.

13. The system of claim 12 wherein the system memory comprises dynamic random access memory (DRAM).

14. The system of claim 13 wherein the DRAM comprises a high bandwidth memory (HBM).

15. The system of claim 9 wherein a first portion of the HPAs are to identify regions of the system memory and a second portion of the HPAs are to identify regions of a graphics processor memory, the graphics processor including the plurality of graphics processing resources.

16. The system of claim 15 wherein the graphics processor memory comprises a high bandwidth memory (HBM) and the system memory comprises a dynamic random access memory (DRAM) or an HBM.

Assignees

• Cooray Niranjan L
• Appu Abhishek R
• Koker Altug
• Ray Joydeep
• Vembu Balaji
• K Pattabhiraman
• Puffer David
• Cowperthwaite David J
• Sankaran Rajesh M
• Singh Satyeshwar
• Kp Sameer
• Shah Ankur N
• Tian Kun
• Intel Corp

Inventors

• Cooray Niranjan L
• Appu Abhishek R
• Koker Altug
• Ray Joydeep
• Vembu Balaji
• K Pattabhiraman
• Puffer David
• Cowperthwaite David J
• Sankaran Rajesh M
• Singh Satyeshwar
• Kp Sameer
• Shah Ankur N
• Tian Kun

Classifications

• G06F13/16 Primary

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/1036

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title