Apparatus and method for memory management in a graphics processing environment

Patent metadata

Field	Value
Publication number	US-2018293183-A1
Application number	US-201715482690-A
Country	US
Kind code	A1
Filing date	Apr 7, 2017
Priority date	Apr 7, 2017
Publication date	Oct 11, 2018
Grant date	—

Abstract

An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

First claim

What is claimed is:

1 . An apparatus comprising:
a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

2 . The apparatus as in claim 1 wherein the system-level MMU comprises an input/output memory management unit (IOMMU).

3 . The apparatus as in claim 1 wherein the second MMU comprises transaction routing circuitry to route the memory transaction to the first MMU, the first MMU comprising transaction routing circuitry to route the memory transaction to the system-level MMU if necessary.

4 . The apparatus as in claim 3 wherein the first MMU includes a first translation lookaside buffer and the second MMU includes a second TLB, wherein upon a translation request from one of the second plurality of graphics processing resources, the second MMU first attempts to perform an address translation from the second TLB and sends the translation request to the first TLB if the address translation is not in the second TLB.

5 . The apparatus as in claim 4 wherein the first MMU is to perform a page walk operation via the system-level MMU if the translation is not stored in the first TLB.

6 . The apparatus as in claim 3 wherein an ID code is embedded in a field of each memory transaction to uniquely identify the MMU from which it originated, the transaction routing circuitry of the first MMU to use the ID code in a response received from the system-level MMU to route the transaction to the second MMU.

7 . The apparatus as in claim 6 wherein the first MMU and the second MMU each includes a data cache, wherein the second MMU will determine whether data requested by the second plurality of graphics processing resources is stored in its data cache before requesting the data from the first MMU.

8 . The apparatus as in claim 7 wherein the first MMU is to determine whether the requested data is stored in its data cache before requesting the data from the system-level MMU.

9 . A method comprising:
executing graphics commands and processing graphics data on a first plurality of graphics processing resources, the first plurality of graphics processing resources being coupled to a system-level MMU to access a system memory via a first memory management unit (MMU); executing graphics commands and processing graphics data on a second plurality of graphics processing resources the, second plurality of graphics processing resources being coupled to the first MMU via a second MMU; configuring the first MMU as a master MMU having a direct connection to the system-level MMU; configuring the second MMU as a slave MMU configured to send memory transactions to the first MMU; servicing a memory transaction generated by the second MMU at the first MMU, the first MMU sending the memory transaction to the system-level MMU on behalf of the second MMU if the first MMU cannot service the request itself.

10 . The method as in claim 9 wherein the system-level MMU comprises an input/output memory management unit (IOMMU).

11 . The method as in claim 9 wherein the second MMU comprises transaction routing circuitry to route the memory transaction to the first MMU, the first MMU comprising transaction routing circuitry to route the memory transaction to the system-level MMU if necessary.

12 . The method as in claim 11 wherein the first MMU includes a first translation lookaside buffer and the second MMU includes a second TLB, wherein upon a translation request from one of the second plurality of graphics processing resources, the second MMU first attempts to perform an address translation from the second TLB and sends the translation request to the first TLB if the address translation is not in the second TLB.

13 . The method as in claim 12 wherein the first MMU is to perform a page walk operation via the system-level MMU if the translation is not stored in the first TLB.

14 . The method as in claim 11 wherein an ID code is embedded in a field of each memory transaction to uniquely identify the MMU from which it originated, the transaction routing circuitry of the first MMU to use the ID code in a response received from the system-level MMU to route the transaction to the second MMU.

15 . The method as in claim 14 wherein the first MMU and the second MMU each includes a data cache, wherein the second MMU will determine whether data requested by the second plurality of graphics processing resources is stored in its data cache before requesting the data from the first MMU.

16 . The method as in claim 15 wherein the first MMU is to determine whether the requested data is stored in its data cache before requesting the data from the system-level MMU.

17 . A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
executing graphics commands and processing graphics data on a first plurality of graphics processing resources, the first plurality of graphics processing resources being coupled to a system-level MMU to access a system memory via a first memory management unit (MMU); executing graphics commands and processing graphics data on a second plurality of graphics processing resources the, second plurality of graphics processing resources being coupled to the first MMU via a second MMU; configuring the first MMU as a master MMU having a direct connection to the system-level MMU; configuring the second MMU as a slave MMU configured to send memory transactions to the first MMU; servicing a memory transaction generated by the second MMU at the first MMU, the first MMU sending the memory transaction to the system-level MMU on behalf of the second MMU if the first MMU cannot service the request itself.

18 . The method as in claim 17 wherein the system-level MMU comprises an input/output memory management unit (IOMMU).

19 . The method as in claim 17 wherein the second MMU comprises transaction routing circuitry to route the memory transaction to the first MMU, the first MMU comprising transaction routing circuitry to route the memory transaction to the system-level MMU if necessary.

20 . The method as in claim 19 wherein the first MMU includes a first translation lookaside buffer and the second MMU includes a second TLB, wherein upon a translation request from one of the second plurality of graphics processing resources, the second MMU first attempts to perform an address translation from the second TLB and sends the translation request to the first TLB if the address translation is not in the second TLB.

21 . The method as in claim 20 wherein the first MMU is to perform a page walk operation via the system-level MMU if the translation is not stored in the first TLB.

22 . The method as in claim 19 wherein an ID code is emb

Assignees

• Intel Corp

Inventors

• Cooray Niranjan L
• Appu Abhishek R
• Koker Altug
• Ray Joydeep
• Vembu Balaji
• K Pattabhiraman
• Puffer David
• Cowperthwaite David J
• Sankaran Rajesh M
• Singh Satyeshwar
• Kp Sameer
• Shah Ankur N
• Tian Kun

Classifications

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F13/4068

  Electrical coupling · CPC title