Spurious junction prevention via in-situ ion milling

US11765985B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11765985-B2
Application numberUS-202016908120-A
CountryUS
Kind codeB2
Filing dateJun 22, 2020
Priority dateJun 22, 2020
Publication dateSep 19, 2023
Grant dateSep 19, 2023

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier. In various embodiments, the shadow evaporation process can further comprise depositing a first superconducting material on the substrate after the patterning the resist stack, oxidizing a surface of the first superconducting material to form the tunnel barrier, and depositing a second superconducting material over the protected portion of the tunnel barrier to form a Josephson junction. In various instances, the etching the exposed portion of the tunnel barrier can occur after the oxidizing the surface of the first superconducting material and before the depositing the second superconducting material.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process, wherein the tunnel barrier is sandwiched between two superconductors; and etching an exposed portion of the tunnel barrier during the shadow evaporation process, wherein the shadow evaporation process comprises: patterning a resist stack onto the substrate, wherein the etching the exposed portion of the tunnel barrier leaves a protected portion of the tunnel barrier within a shadow of the resist stack, wherein the two superconductors comprise a first superconductor having a first superconducting material and a second superconductor having a second superconducting material and wherein the shadow evaporation process further comprises: depositing the first superconducting material on the substrate after the patterning the resist stack; oxidizing a surface of the first superconducting material to form the tunnel barrier; and depositing the second superconducting material over the protected portion of the tunnel barrier to form the Josephson junction, wherein the etching the exposed portion of the tunnel barrier occurs after the oxidizing the surface of the first superconducting material and before the depositing the second superconducting material. 2. The method of claim 1 , wherein the resist stack includes a suspended resist bridge, and wherein the protected portion of the tunnel barrier is beneath the suspended resist bridge. 3. The method of claim 1 , wherein the etching the exposed portion of the tunnel barrier employs ion milling. 4. The method of claim 3 , wherein a duration of the oxidizing the surface of the first superconducting material is based on a duration of the ion milling. 5. The method of claim 3 , wherein the shadow evaporation process is a Dolan double angle evaporation technique, and wherein the ion milling is performed in a top-down direction. 6. A method, comprising: patterning a bi-layer resist stack on a substrate; forming a junction barrier layer on a first superconductor on the substrate during a shadow evaporation technique; and directionally etching a first portion of the junction barrier layer during the shadow evaporation technique, the first portion being outside of a shadow cast by the bi-layer resist stack, wherein the junction barrier layer is disposed between the first superconductor and a second superconductor, wherein the shadow evaporation technique comprises: evaporating the first superconductor onto the substrate; oxidizing a surface of the first superconductor to form the junction barrier layer; and evaporating the second superconductor over the second portion of the junction barrier layer, wherein directionally etching the first portion of the junction barrier layer occurs after the oxidizing the surface of the first superconductor and before the evaporating the second superconductor. 7. The method of claim 6 , wherein the directionally etching the first portion of the junction barrier layer causes a second portion of the junction barrier layer to remain on the first superconductor, the second portion being inside the shadow cast by the bi-layer resist stack. 8. The method of claim 7 , wherein the bi-layer resist stack includes a bridge, and wherein the second portion of the junction barrier layer lies beneath the bridge. 9. The method of claim 6 , wherein the directionally etching the first portion of the junction barrier layer employs ion milling. 10. The method of claim 9 , wherein a duration of the oxidizing the surface of the first superconductor is based on a duration of the ion milling. 11. The method of claim 9 , wherein the shadow evaporation technique is a Dolan double evaporation technique, and wherein the ion milling is performed in a top-down direction.

Assignees

Inventors

Classifications

  • H10N60/12Primary

    Josephson-effect devices · CPC title

  • of Josephson-effect devices · CPC title

  • for Josephson-effect devices · CPC title

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What does patent US11765985B2 cover?
Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10N60/12. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 19 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).