Drift compensation

US11764731B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11764731-B2
Application numberUS-202218059812-A
CountryUS
Kind codeB2
Filing dateNov 29, 2022
Priority dateFeb 21, 2020
Publication dateSep 19, 2023
Grant dateSep 19, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: operating a quartz crystal and oscillator circuit to provide a clock signal having a center frequency to an integrated circuit; disabling a power amplifier of the integrated circuit; turning on a heater to increase a temperature of the quartz crystal; turning off the heater after a first duration; and after turning off the heater, enabling the power amplifier to emit a radio frequency (RF) signal. 2. The method of claim 1 , further comprising: generating, by a control circuit of the integrated circuit, a first control signal to turn on and turn off the heater; and generating, by the control circuit, a second control signal to enable and disable the power amplifier. 3. The method of claim 1 , wherein the heater is a resistor, and the turning on the heater comprises: sending a current through the resistor to increase heat dissipated by the resistor. 4. The method of claim 3 , further comprising setting a resistance value of the resistor to be between 50 Ohms and 150 Ohms. 5. The method of claim 4 , further comprising locating the heater less than 10 mm away from the quartz crystal. 6. The method of claim 1 , wherein increasing the temperature of the quartz crystal decreases a drift absolute value of the clock signal center frequency. 7. The method of claim 6 , wherein turning off the heater and enabling the power amplifier offset each other to maintain a decreased drift absolute value of the clock signal center frequency. 8. The method of claim 1 , further comprising delaying for a second duration between turning off the heater and enabling the power amplifier. 9. The method of claim 1 , further comprising: after enabling the power amplifier, delaying for a third duration; and after the third duration, enabling a passage of the RF signal from the power amplifier to an antenna. 10. The method of claim 9 , further comprising selecting the third duration based on a second temperature measured by a temperature sensor of the integrated circuit. 11. The method of claim 10 , wherein the second temperature measured by the temperature sensor is indicative of an ambient temperature or an integrated circuit temperature. 12. The method of claim 9 , further comprising: generating, by a control circuit of the integrated circuit, a single control signal to enable the power amplifier and the passage of the RF signal from the power amplifier to the antenna; and adding the third duration to the single control signal before the single control signal reaches a switch coupled between the power amplifier and the antenna. 13. The method of claim 12 , wherein the third duration is greater than 5 ms. 14. A method comprising: operating a quartz crystal and oscillator circuit to provide a clock signal having a center frequency to an integrated circuit; disabling a power amplifier of the integrated circuit; turning on a heater to increase a temperature of the quartz crystal, by sending a current through a resistor to increase heat dissipated by the resistor; turning off the heater after a first duration; after turning off the heater, enabling the power amplifier to emit a radio frequency (RF) signal; and after enabling the power amplifier, delaying for a third duration; and after the third duration, enabling a passage of the RF signal from the power amplifier to an antenna. 15. The method of claim 14 , further comprising: generating, by a control circuit of the integrated circuit, a first control signal to turn on and turn off the heater; and generating, by the control circuit, a second control signal to enable and disable the power amplifier. 16. The method of claim 14 , wherein increasing the temperature of the quartz crystal decreases a drift absolute value of the clock signal center frequency. 17. The method of claim 16 , wherein turning off the heater and enabling the power amplifier offset each other to maintain a decreased drift absolute value of the clock signal center frequency. 18. The method of claim 14 , further comprising delaying for a second duration between turning off the heater and enabling the power amplifier. 19. The method of claim 14 , further comprising selecting the third duration based on a second temperature measured by a temperature sensor of the integrated circuit. 20. The method of claim 14 , further comprising: generating, by a control circuit of the integrated circuit, a single control signal to enable the power amplifier and the passage of the RF signal from the power amplifier to the antenna; and adding the third duration to the single control signal before the single control signal reaches a switch coupled between the power amplifier and the antenna.

Assignees

Inventors

Classifications

  • H03F1/30Primary

    Modifications of amplifiers to reduce influence of variations of temperature or supply voltage {or other physical parameters (in differential amplifiers H03F3/45479)} · CPC title

  • H03L1/02Primary

    against variations of temperature only · CPC title

  • H03B5/36Primary

    active element in amplifier being semiconductor device ({H03B5/323, H03B5/326} , H03B5/38 take precedence) · CPC title

  • Modifications of amplifiers to reduce non-linear distortion (by negative feedback H03F1/34) · CPC title

  • by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature (H03L1/021 takes precedence) · CPC title

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Frequently asked questions

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What does patent US11764731B2 cover?
The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
Who is the assignee on this patent?
St Microelectronics Alps Sas, St Microelectronics Grenoble 2, St Microelectronics Rousset, and 1 more
What technology area does this patent fall under?
Primary CPC classification H03F1/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 19 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).