Method for re-centering a VCO, integrated circuit and wireless device

Patent metadata

Field	Value
Publication number	US-9515666-B2
Application number	US-201514606492-A
Country	US
Kind code	B2
Filing date	Jan 27, 2015
Priority date	Aug 27, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A method of re-centering a voltage controlled oscillator of a wireless device comprising a phase locked loop circuit is described. The method comprises receiving an input frequency signal at a phase detector of the phase locked loop circuit from a frequency source; generating an oscillator signal based on the received frequency signal; selectably opening a feedback loop of the phase locked loop circuit when in a calibration mode of operation, performing coarse frequency tuning of the oscillator output signal; performing fine frequency tuning of a coarsely adjusted oscillator output signal; and closing the feedback loop.

First claim

The invention claimed is:

1. A method of re-centering a voltage controlled oscillator of a wireless device comprising a phase locked loop circuit, the method comprising:
receiving an input frequency signal at a phase detector of the phase locked loop circuit from a frequency source;
generating an oscillator signal based on the received frequency signal;
selectably opening a feedback loop of the phase locked loop circuit when in a calibration mode of operation;
performing coarse frequency tuning of the oscillator output signal, wherein performing coarse frequency tuning comprises applying a coarse tuning control signal to switch a number of selectable first capacitive elements in the coarse tuning capacitive circuit in or out of the oscillator, and wherein applying the coarse tuning control signal comprises switching selectable first capacitive elements in or out of the oscillator until a first minimum oscillator frequency error is determined, and fixing the coarse tuning capacitive circuit arrangement with the first minimum determined oscillator frequency error;
performing fine frequency tuning of a coarsely adjusted oscillator output signal, wherein performing fine frequency tuning comprises applying a fine tuning control signal to switch a number of selectable second capacitive elements in a fine tuning capacitive circuit in or out of the oscillator; and
closing the feedback loop.

2. The method of claim 1 wherein applying the fine tuning control signal comprises:
switching selectable second capacitive elements in or out of the oscillator until a second minimum oscillator frequency error is determined; and
fixing the fine tuning capacitive circuit arrangement with the second minimum determined oscillator frequency error.

3. The method of claim 2 wherein the fine tuning capacitive circuit arrangement comprises a main bank of selectable first capacitive elements and at least one shunt bank of selectable second capacitive elements located between ground and one of an input node or an output node of the fine tuning capacitive circuit arrangement, switching a number of selectable second capacitive elements out of the oscillator comprises switching at least one selectable second capacitive element out of the oscillator based on a number of the selectable first capacitive elements that are switched into the oscillator.

4. The method of claim 2 wherein the at least one selectable second capacitive element switched out of the oscillator is configured to maintain a constant capacitance adjustment step independent of the number of the selectable first capacitive elements that are switched into the oscillator.

5. The method of claim 1 wherein performing fine frequency tuning of the oscillator output signal comprises:
applying a first control signal comprising a control word to a main capacitive bank of selectable fine tuning capacitive elements; and
applying a second control signal comprising an inverted representation of the control word to at least one shunt bank of selectable second capacitive elements.

6. The method of claim 1 further comprising setting the coarse tuning capacitive circuit and the fine tuning capacitive circuit to a mid-range capacitance value prior to commencing a calibration mode of operation.

7. An integrated circuit comprising a phase locked loop circuit coupled to a digital controller, the phase locked loop circuit comprising:
an input;
an output;
a phase detector configured to receive an input frequency signal from a frequency source;
an oscillator configured to receive a frequency signal from the phase detector and generate an oscillator signal, wherein the oscillator comprises a coarse tuning capacitive circuit and a fine tuning capacitive circuit coupled in parallel to the oscillator and configured to adjust a frequency of the generated oscillator signal;
a feedback loop coupled to the digital controller and configured to couple the output to the phase detector via a divider; wherein in a calibration mode of operation of the phase locked loop circuit, the feedback loop is configured to be selectably opened by the digital controller to allow coarse frequency tuning of the oscillator output signal by the coarse tuning capacitive circuit followed by fine frequency tuning of a coarsely adjusted oscillator output signal by the fine tuning capacitive circuit, and wherein the digital controller is configured to:
apply a coarse tuning control signal to switch a number of selectable first capacitive elements in the coarse tuning capacitive circuit in or out of the oscillator;
adjust the coarse tuning capacitive circuit by applying the coarse tuning control signal to switch a number of selectable first capacitive elements in or out of the oscillator until a first minimum oscillator frequency error is determined;
fix the coarse tuning capacitive circuit arrangement with the first minimum determined oscillator frequency error; and
apply a fine tuning control signal to switch a number of selectable second capacitive elements in the fine tuning capacitive circuit in or out of the oscillator.

8. The integrated circuit of claim 7 wherein the digital controller is further operably coupled to the coarse tuning capacitive circuit and fine tuning capacitive circuit and configured to selectably insert or remove capacitive elements in at least one of the coarse tuning capacitive circuit and fine tuning capacitive circuit in order to adjust a frequency of the generated oscillator signal.

9. The device of claim 7 wherein the digital controller comprises a comparator configured to receive and compare a divided down representation of the oscillator output signal with an injected reference signal, to determine an accuracy of the oscillator output signal.

10. The integrated circuit of claim 7 wherein the digital controller is configured to, using the fixed coarse tuning capacitive circuit arrangement:
adjust the fine tuning capacitive circuit by applying the fine tuning control signal to switch a number of selectable second capacitive elements in or out of the oscillator until a second minimum oscillator frequency error is determined; and
fix the fine tuning capacitive circuit arrangement with the second minimum determined oscillator frequency error.

11. The integrated circuit of claim 7 wherein the digital controller is operably coupled to memory and the memory is configured to store the coarse tuning control signal.

12. The integrated circuit of claim 7 wherein the fine tuning capacitive circuit comprises a main capacitive bank comprising a number of selectable fine tuning capacitive elements and at least one shunt bank of selectable second capacitive elements.

13. The integrated circuit of claim 12 wherein the fine tuning control signal comprises a first control signal comprising a control word and the digital controller is configured to apply the first control signal comprising a control word to the main capacitive bank of selectable fine tuning capacitive elements and a second control signal comprising an inverted representation of the control word to the at least one shunt bank of selectable second capacitive elements.

14. A wireless device comprising a phase locked loop circuit that comprises:
an input;
an output;
a phase detector configured to receive an input frequency signal from a frequency source;
an oscillator configured to receive a frequency signal from the phase detector and generate an oscillator signal, wherein the oscillator comprises a coarse tuning capacitive circuit and a fine tuning capacitive circuit coupled in parallel to the oscillator and configured to adjust a frequency of the generate

Assignees

• Pavao-Moreira Cristian
• Goumballa Birama
• Yin Yi
• Freescale Semiconductor Inc

Inventors

• Pavao-Moreira Cristian
• Goumballa Birama
• Yin Yi

Classifications

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03B5/1215

  the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title