Clock generator using free-running oscillator and method therefor

Patent metadata

Field	Value
Publication number	US-9356606-B2
Application number	US-201414339113-A
Country	US
Kind code	B2
Filing date	Jul 23, 2014
Priority date	Jul 23, 2014
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A clock generator comprises a free-running oscillator and a tunable frequency synthesizer. The free-running oscillator has an output for providing an oscillator clock signal. The tunable frequency synthesizer is coupled to the free-running oscillator and provides a clock output signal in response to the oscillator clock signal and a frequency control signal. The frequency control signal corresponds to a measured characteristic of the free-running oscillator.

First claim

What is claimed is:

1. A clock generator comprising:
a free-running LC oscillator having an output for providing an oscillator clock signal;
a tunable frequency synthesizer coupled to said free-running oscillator for providing a clock output signal in response to said oscillator clock signal and a frequency control signal, said frequency control signal corresponding to a measured characteristic of said free-running oscillator, wherein said tunable frequency synthesizer comprises a compensation processor for providing said frequency control signal based on said measured characteristic and a frequency select signal; and
a calibration circuit coupled to said tunable frequency synthesizer for providing a frequency offset signal corresponding to an offset in frequency between said oscillator clock signal and a reference clock signal as said measured characteristic in response to said compensation processor.

2. The clock generator of claim 1 , further comprising:
a temperature sensor thermally coupled to said free-running LC oscillator for providing a temperature signal representative of a temperature of said free-running oscillator as said measured characteristic to said compensation processor.

3. The clock generator of claim 2 , wherein said calibration circuit comprises:
a non-volatile memory coupled to said tunable frequency synthesizer for storing said frequency offset signal and providing said frequency offset signal so stored to said tunable frequency synthesizer; and
a calibration controller coupled to said tunable frequency synthesizer, for forming said frequency offset signal and storing said frequency offset signal so formed in said non-volatile memory.

4. The clock generator of claim 3 , wherein said calibration circuit further comprises:
an integrated circuit terminal adapted to receive said reference clock signal.

5. A clock generator comprising:
a free-running LC oscillator having an output for providing an oscillator clock signal; and
a tunable frequency synthesizer coupled to said free-running oscillator for providing a clock output signal in response to said oscillator clock signal and a frequency control signal, said frequency control signal corresponding to a measured characteristic of said free-running oscillator, said tunable frequency synthesizer comprising:
a compensation processor for providing said frequency control signal based on said measured characteristic and a frequency select signal, comprising a modulator having an input for receiving a data signal, and an output for providing a modulated data signal,
wherein said compensation processor further provides said frequency control signal in response to said modulated data signal.

6. An integrated circuit comprising:
a free-running oscillator having an output for providing an oscillator clock signal with an oscillation frequency set using an inductor and a capacitor;
a tunable frequency synthesizer having a first input for receiving said oscillator clock signal, a second input for receiving a frequency control signal, and an output for providing a clock output signal, wherein said tunable frequency synthesizer provides said clock output signal in response to said oscillator clock signal and said frequency control signal, and comprising a compensation processor for providing said frequency control signal based on a measured characteristic and a frequency select signal;
a functional circuit having an input for receiving said clock output signal; and
a calibration circuit coupled to said tunable frequency synthesizer for providing a frequency offset signal corresponding to an offset in frequency between said oscillator clock signal and a reference clock signal as said measured characteristic in response to said compensation processor.

7. The integrated circuit of claim 6 , wherein said calibration circuit comprises:
a non-volatile memory coupled to said tunable frequency synthesizer for storing said frequency offset signal and providing said frequency offset signal so stored to said tunable frequency synthesizer; and
a calibration controller coupled to said tunable frequency synthesizer, for forming said frequency offset signal and storing said frequency offset signal so formed in said non-volatile memory.

8. The integrated circuit of claim 7 , wherein said calibration circuit further comprises:
an integrated circuit terminal adapted to received said reference clock signal.

9. The integrated circuit of claim 6 , wherein said functional circuit comprises:
a jitter cleaning phase locked loop having a first input for receiving a clock input signal, a second input for receiving said clock output signal, and an output for providing said frequency control signal in response to a deviation between said clock input signal and said clock output signal.

10. A clock generator comprising:
a free-running oscillator having an output for providing an oscillator clock signal;
a tunable frequency synthesizer coupled to said free-running oscillator for providing a clock output signal in response to said oscillator clock signal and a frequency control signal;
a compensation processor having a first input for receiving a temperature signal, and a second input for receiving a frequency offset signal, wherein said compensation processor provides said frequency control signal in response to both said temperature signal and said frequency offset signal; and
a calibration circuit coupled to said tunable frequency synthesizer for providing said frequency offset signal corresponding to an offset in frequency between said oscillator clock signal and a reference clock signal.

11. The clock generator of claim 10 , further comprising:
a temperature sensor thermally coupled to said free-running oscillator for providing said temperature signal in response to a temperature of said free-running oscillator.

12. The clock generator of claim 10 , wherein said calibration circuit comprises:
a non-volatile memory coupled to said tunable frequency synthesizer for storing said frequency offset signal and providing said frequency offset signal so stored to said tunable frequency synthesizer; and
a calibration controller coupled to said tunable frequency synthesizer, for forming said frequency offset signal and storing said frequency offset signal so formed in said non-volatile memory.

13. The clock generator of claim 10 , wherein said calibration circuit comprises:
an integrated circuit terminal adapted to receive said reference clock signal.

14. The clock generator of claim 10 , wherein said compensation processor further provides said frequency control signal in response to a modulated data signal.

15. The clock generator of claim 14 , wherein said compensation processor comprises:
a modulator having an input for receiving said data signal, and an output for providing said modulated data signal.

16. The clock generator of claim 15 , wherein said modulator further has an input for receiving a deviation setting signal, and wherein said modulator further varies said modulated data signal in an amount corresponding to said deviation setting signal based on states of said data signal.

17. The clock generator of claim 10 , wherein said compensation processor comprises:
a polynomial compensation processor having a first input for receiving said temperature signal, a second input for receiving said frequency offset signal, and an output, wherein said compensation processor provides said frequency control signal in response to said output.

18. The clock generator of claim 17 , wherein said compen

Assignees

• Silicon Lab Inc

Inventors

• Caffee Aaron J
• Drost Brian G
• De Ruijter Hendricus

Classifications

• H03L1/026

  by using a memory for digitally storing correction values (H03L1/025 takes precedence) · CPC title

• H03B5/12 Primary

  active element in amplifier being semiconductor device (H03B5/14 takes precedence) · CPC title

• H03L7/02

  using a frequency discriminator comprising a passive frequency-determining element · CPC title

• H03B1/00

  Details · CPC title

• H03L1/00 Primary

  Stabilisation of generator output against variations of physical values, e.g. power supply · CPC title