Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11764272-B2
Application number	US-202117321602-A
Country	US
Kind code	B2
Filing date	May 17, 2021
Priority date	May 20, 2020
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

The disclosure relates to a semiconductor device having a first active region, a plurality of elongated gate regions having an elongated extension in a first lateral direction, respectively, a plurality of elongated field plate regions having an elongated extension in the first lateral direction, respectively, and a first additional gate region, wherein a first one of the elongated gate regions is arranged in a first elongated gate trench at a first side of the first active region, and a second one of the elongated gate regions is arranged in a second elongated gate trench at a second side of the first active region, the second side lying opposite to the first side with respect to a second lateral direction, and wherein the first additional gate region is arranged in a first additional gate trench which extends at least proportionately in the second lateral direction through the first active region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first active region;
a plurality of elongated gate regions having an elongated extension in a first lateral direction, respectively;
a plurality of elongated field plate regions having an elongated extension in the first lateral direction, respectively; and
a first additional gate region,
wherein a first one of the elongated gate regions is arranged in a first elongated gate trench at a first side of the first active region,
wherein a second one of the elongated gate regions is arranged in a second elongated gate trench at a second side of the first active region, the second side lying opposite to the first side with respect to a second lateral direction,
wherein the first additional gate region is arranged in a first additional gate trench which extends at least proportionately in the second lateral direction through the first active region.

2. The semiconductor device of claim 1 , wherein at least a portion of the first additional gate trench extends laterally in parallel to the second lateral direction.

3. The semiconductor device of claim 1 , wherein at least a portion of the first additional gate trench extends laterally at an angle α of 10° at minimum and 80° at maximum to the second lateral direction.

4. The semiconductor device of claim 1 , wherein a first portion of the first additional gate trench extends laterally at a first angle α 1 to the second lateral direction and a second portion of the first additional gate trench extends laterally at a second angle α 2 to the second lateral direction, and wherein the angles α 1 and α 2 are different from each other.

5. The semiconductor device of claim 4 , wherein a bend between the first portion and the second portion of the first additional gate trench is arranged laterally between the first elongated gate trench and the second elongated gate trench.

6. The semiconductor device of claim 1 , further comprising a second additional gate region arranged in a second additional gate trench which extends at least proportionately in the second lateral direction through the first active region.

7. The semiconductor device of claim 6 , wherein a first one of the elongated field plate regions is arranged in the first elongated gate trench below the first elongated gate region, wherein a second one of the elongated field plate regions is arranged in the second elongated gate trench below the second elongated gate region, wherein the first elongated gate trench and the second elongated gate trench delimit the first active region in the first lateral direction, and wherein the first additional gate trench and the second additional gate trench delimit the first active region in the second lateral direction.

8. The semiconductor device of claim 7 , wherein in a plan view in a vertical direction perpendicular to the first lateral direction and the second lateral direction, the first active region has a trapezoidal shape with two parallel sides defined by the first elongated gate trench and the second elongated gate trench and two non-parallel sides defined by the first additional gate trench and the second additional gate trench.

9. The semiconductor device of claim 1 , further comprising a second additional gate region arranged in a second additional gate trench, wherein at least a portion of the first additional gate trench extends at a third angle α 3 to the second lateral direction and at least a portion of the second additional gate trench extends at a fourth angle α 4 to the second lateral direction, and wherein the angles α 3 and α 4 are different from each other.

10. The semiconductor device of claim 1 , further comprising a plurality of additional gate regions which are respectively arranged in an additional gate trench, wherein the plurality of additional gate trenches are distributed laterally over the semiconductor device with a varying areal density.

11. The semiconductor device of claim 1 , wherein a first one of the field plate regions is arranged in the first elongated gate trench below the first gate region, and wherein a second one of the field plate regions is arranged in the second elongated gate trench below the second gate region.

12. The semiconductor device of claim 1 , wherein in a vertical direction perpendicular to the first lateral direction and the second lateral direction, the first elongated gate trench and the second elongated gate trench extend deeper than the first additional gate trench.

13. The semiconductor device of claim 1 , wherein the first additional gate region connects the first elongated gate region and the second elongated gate region to one another.

14. The semiconductor device of claim 1 , wherein in a vertical direction perpendicular to the first lateral direction and the second lateral direction, the plurality of elongated field plate regions extend deeper than the first additional gate region.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Laforet David
• Braz Cesar Augusto
• Ferrara Alessandro
• Ouvrard Cédric
• Yip Li Juin

Classifications

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title