Power semiconductor device having different gate crossings, and method for manufacturing thereof

Patent metadata

Field	Value
Publication number	US-10629595-B2
Application number	US-201816020133-A
Country	US
Kind code	B2
Filing date	Jun 27, 2018
Priority date	Jun 29, 2017
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

A power semiconductor device includes a semiconductor substrate having a first side. A plurality of active transistor cells is formed in an active area of the semiconductor substrate. Each of the plurality of active transistor cells includes a spicular trench which extends from the first side into the semiconductor substrate and has a field electrode. A gate electrode structure has a plurality of intersecting gate trenches running between the spicular trenches. The intersecting gate trenches form gate crossing regions of different shape when seen in a plan projection onto the first side of the power semiconductor device.

First claim

What is claimed is:

1. A power semiconductor device, comprising: a semiconductor substrate having a first side;
a plurality of active transistor cells formed in an active area of the semiconductor substrate, each of the plurality of active transistor cells comprising a spicular trench which extends from the first side into the semiconductor substrate and comprises a field electrode; and
a gate electrode structure comprising a plurality of intersecting gate trenches running between the spicular trenches,
wherein the plurality of intersecting gate trenches comprises a plurality of first gate crossing regions and a plurality of second gate crossing regions, each of the first gate crossing regions comprising a first wall section, each of the second gate crossing regions comprising a second wall section,

wherein the first wall section forms a transition that joins two transverse gate trench spans together,
wherein the second wall section forms a transition that joins two transverse gate trench spans together,
wherein when seen in a plan projection onto the first side of the semiconductor substrate, the first wall section has a first radius and the second wall section has a second radius that is different from the first radius.

2. The power semiconductor device of claim 1 , wherein, when seen in the plan projection onto the first side, each of the first gate crossing regions defines a round transition between intersecting gate trenches with the first radius and each of the second gate crossing regions defines a sharp transition between intersecting gate trenches with the second radius, the sharp transition being relatively sharper in comparison to the round transition.

3. The power semiconductor device of claim 2 , wherein the first radius is at least twice as large as the second radius.

4. The power semiconductor device of claim 2 , wherein a total number of the first gate crossing regions between intersecting gate trenches is equal to or higher than a total number of the second gate crossing regions between intersecting gate trenches in the active area.

5. The power semiconductor device of claim 2 , wherein a total number of the first gate crossing regions between intersecting gate trenches is between 50% and 90% of a total number of the first gate crossing regions and the second gate crossing regions in the active area.

6. The power semiconductor device of claim 2 , wherein a total number of the first gate crossing regions between intersecting gate trenches is between 60% and 80% of a total number of the first gate crossing regions and the second gate crossing regions in the active area.

7. The power semiconductor device of claim 2 , wherein the gate crossing regions further comprises third gate crossing regions, wherein, when seen in the plan projection onto the first side, each of third gate crossing regions defines a round transition between intersecting gate trenches with a third radius, and wherein the third radius is smaller than the first radius and larger than the second radius.

8. The power semiconductor device of claim 1 , wherein the gate electrode structure comprises a gate dielectric between a gate electrode and the semiconductor substrate, and wherein the gate dielectric has substantially the same thickness in the gate crossing regions of different shape.

9. The power semiconductor device of claim 1 , wherein each active transistor cell comprises a body region and a gate electrode in a respective gate trench of the gate electrode structure.

10. The power semiconductor device of claim 1 , wherein the second gate crossing defines a local threshold voltage having an absolute value which is about 60% to 80% of an absolute value of a local threshold voltage of the first gate crossings.

11. A power semiconductor device, comprising: a semiconductor substrate having a first side and an active area;
a plurality of spaced apart spicular trenches in the active area and extending from the first side into the semiconductor substrate, each of the spicular trenches comprising a field electrode; and
a plurality of intersecting gate trenches between adjacent spicular trenches,
wherein, when seen in a plan projection onto the first side, the plurality of the intersecting gate trenches form a grid structure with a plurality of grid meshes to surround respective spicular trenches,
wherein the gate trenches comprise respective gate electrodes, are adjacent to body regions and define channel regions in the body regions,
wherein a respective channel region completely surrounds a respective spicular trench when seen in the plan projection onto the first side of the semiconductor substrate,
wherein at a first one of the grid meshes, a first wall section of the gate trenches joins transverse spans of the gate trenches together,
wherein at a second one of the grid meshes, a second wall section of the gate trenches joins transverse spans of the gate trenches together,
wherein the wall section has a different shape as the second wall section when seen in plan projection onto the first side, and
wherein the plurality of grid meshes comprises first grid meshes having a substantially round boundary and second grid meshes having a partially straight boundary, wherein a percentage ratio of straight span length to curved span length in an enclosed boundary formed by the first grid meshes is greater than a percentage ratio of straight span length to curved span length formed by the second grid meshes.

12. The power semiconductor device of claim 11 , wherein a total number of the first grid meshes is equal to or higher than a total number of the second grid meshes in the active area.

13. The power semiconductor device of claim 11 , wherein a total number of the first grid meshes is between 50% and 90% of a total number of the first grid meshes and the second grid meshes in the active area.

14. The power semiconductor device of claim 11 , wherein a total number of the first grid meshes is between 60% and 80% of a total number of the first grid meshes and the second grid meshes in the active area.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Ouvrard Cedric
• Braz Cesar Augusto
• Guillemant Olivier
• Laforet David
• Noebauer Gerhard
• Yip Li Juin

Classifications

• H01L29/7813

  Electricity · mapped topic

• H01L29/4238

  Electricity · mapped topic

• H01L21/823456

  Electricity · mapped topic

• H01L21/823418

  Electricity · mapped topic

• H01L29/7397

  Electricity · mapped topic