Semiconductor packages, and methods for forming semiconductor packages

Patent metadata

Field	Value
Publication number	US-11764187-B2
Application number	US-201716641241-A
Country	US
Kind code	B2
Filing date	Sep 29, 2017
Priority date	Sep 29, 2017
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first semiconductor die;
a semiconductor device comprising a second semiconductor die, and
one or more wire bond structures, wherein a wire bond structure of the one or more wire bond structures comprises a first and a second bond interface portion and wherein the first and second bond interface portions of the wire bond structure comprise a nail-head structure or a ball structure,
wherein the wire bond structure is arranged next to the first semiconductor die,
wherein the first semiconductor die and the first bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device,
wherein the second bond interface portion of the wire bond structure is electrically connected to the first semiconductor die,
wherein an interface contact structure of the semiconductor device is electrically connected to the first bond interface portion of the wire bond structure, and
wherein the first bond interface portion directly contacts the interface contact structure.

2. The semiconductor package according to claim 1 , wherein the interface contact structure of the semiconductor device comprises a solder structure.

3. The semiconductor package according to claim 1 , wherein the interface contact structure of the semiconductor device is directly soldered to the first bond interface portion of the wire bond structure.

4. The semiconductor package according to claim 1 , wherein the interface contact structure of the semiconductor device is arranged at a level of a back side of the first semiconductor die.

5. The semiconductor package according to claim 1 , further comprising a mold compound structure surrounding at least the wire bond structure and the first semiconductor die.

6. The semiconductor package according to claim 1 , further comprising at least one back side redistribution layer arranged at a back side of the first semiconductor die,
wherein the interface contact structure of the semiconductor device is electrically connected to the first bond interface portion of the wire bond structure via the at least one back side redistribution layer.

7. The semiconductor package according to claim 1 , wherein the second bond interface portion of the wire bond structure is attached to a die pad structure arranged at a front side of the first semiconductor die.

8. The semiconductor package according to claim 1 , further comprising a plurality of interconnect structures extending from a front side of the first semiconductor die towards a plurality of interface solder structures arranged at a first side of the semiconductor package.

9. The semiconductor package according to claim 1 , wherein the first semiconductor die comprises at least one circuit selected from the following group of circuits: a logic circuit, a transistor circuit, a processor circuit.

10. The semiconductor package according to claim 1 , wherein the semiconductor device comprising the second semiconductor die comprises a flip chip semiconductor package.

11. The semiconductor package according to claim 1 , wherein the semiconductor device comprising the second semiconductor die comprises a bare die semiconductor device.

12. The semiconductor package according to claim 1 , wherein the second semiconductor die comprises at least one circuit selected from the following group of circuits: a memory circuit, an antenna circuit, a sensor circuit, an integrated passive components circuit and a transceiver circuit, a logic circuit, a transistor circuit.

13. A method for forming a semiconductor package, the method comprising:
forming a wire bond structure next to a first semiconductor die;
wherein the wire bond structure comprises a first and a second bond interface portion and wherein the first and the second bond interface portions comprise a nail-head structure or a ball structure;
attaching the second bond interface portion of the wire bond structure to a die pad structure of the first semiconductor die;
forming a mold compound structure, wherein the mold compound structure at least partially surrounds the wire bond structure and the first semiconductor die,
wherein a surface of the wire bond structure is located at a corresponding level of a back surface of the first semiconductor die and wherein the surface of the wire bond structure is not surrounded by the mold compound structure; and

attaching a second semiconductor die to the first semiconductor die after forming the mold compound structure by soldering an interface contact structure of the second semiconductor die to the first bond interface portion of the wire bond structure.

14. The method according to claim 13 , further comprising forming an over-mold compound structure around the second semiconductor die after attaching the second semiconductor die.

Assignees

• Intel Corp

Inventors

• Waidhas Bernd
• Seidemann Georg
• Wagner Thomas
• Wolter Andreas
• Augustin Andreas
• Koller Sonja
• Ort Thomas
• Mahnkopf Reinhard

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title