Multi-decks memory device including inter-deck switches

Patent metadata

Field	Value
Publication number	US-11763889-B2
Application number	US-202217706087-A
Country	US
Kind code	B2
Filing date	Mar 28, 2022
Priority date	Dec 21, 2017
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

First claim

What is claimed is:

1. An apparatus comprising:
first memory cells, each the first memory cells including a charge-storage portion;
second memory cells located over the first memory cells, each the second memory cells including a charge-storage portion;
first control gates adjacent the first memory cells;
second control gates adjacent the second memory cells;
a first channel structure extending in a direction from one memory cell to the next memory cell of the first memory cells and separated from the charge-storage portion of each of first memory cells by a first dielectric structure;
a second channel structure extending in a direction from one memory cell to the next memory cell of the second memory cells and separated from the charge-storage portion of each of second memory cells by a second dielectric structure;
an additional control gate located between the first control gates and the second control gates;
a conductive structure located between the first and second channel structures and contacting the first and second channel structures, wherein the conductive structure includes undoped polysilicon; and
an addition dielectric structure between the additional control gate and the conductive structure, the additional dielectric structure contacting the conductive structure and the additional control gate.

2. The apparatus of claim 1 , wherein the first and second channel structures have a same doping concentration.

3. The apparatus of claim 1 , wherein the additional control gate and each of the first and second control gates include a same conductivity type.

4. The apparatus of claim 1 , wherein each of the first and second control gates and the additional control gate have a same thickness.

5. The apparatus of claim 1 , wherein each of the first and second control gates and the additional control gate have different thicknesses.

6. The apparatus of claim 1 , further comprising:
a second additional control gate located between the first control gates and the second control gates, wherein the conductive structure contacts the additional dielectric structure and the second additional control gate.

7. The apparatus of claim 6 , wherein the additional control gate and the second additional control gate are electrically coupled to each other.

8. An apparatus comprising: first memory cells located in different levels in a first portion of the apparatus, each the first memory cells including a charge-storage portion; second memory cells located in different levels in a second portion of the apparatus, each the second memory cells including a charge-storage portion; a switch located in a third portion of the apparatus between the first and second portions; first control gates located in the first portion to access the first memory cells; second control gates located in the second portion to access the second memory cells; an additional control gate to control the switch, the additional control gate located between the first control gates and the second control gates; a first conductive structure extending in a direction from one memory cell to a next memory cell among the first memory cells; a first dielectric structure between the first conductive structure and the charge-storage portion of each of first memory cells; an undoped polysilicon structure contacting the first conductive structure and separated from a sidewall of the additional control gate; and a second dielectric structure between the undoped polysilicon structure and the sidewall of the additional control gate.

9. The apparatus of claim 8 , wherein the additional control gate and each of the first and second control gates include conductively doped semiconductor material of a same conductivity type.

10. The apparatus of claim 8 , wherein the additional control gate and each of the first and second control gates include N− doped polysilicon.

11. The apparatus of claim 8 , wherein the first conductive structure includes doped polysilicon.

12. The apparatus of claim 8 , wherein:
the additional control gate has a first thickness in a direction parallel to a direction from the first memory cells to the second memory cells;
each of the first and second control gates has a second thickness in the direction parallel to the direction from the first memory cells to the second memory cells; and
the first thickness is the same as the second thickness.

13. The apparatus of claim 8 , wherein:
the additional control gate has a first thickness in a direction parallel to a direction from the first memory cells to the second memory cells;
each of the first and second control gates has a second thickness in the direction parallel to the direction from the first memory cells to the second memory cells; and
the first thickness is greater than the second thickness.

14. The apparatus of claim 8 , wherein the switch includes a structure of a transistor, and the second dielectric structure is part of a gate dielectric of the transistor.

15. The apparatus of claim 8 , wherein the charge-storage portion of each the first memory cells includes polysilicon.

16. The apparatus of claim 8 , further comprising at least one additional switch located between the first memory cells and the second memory cells.

17. An apparatus comprising:
a first deck of first memory cells in a memory device, the first deck including a first channel structure extending through the first memory cells;
a second deck of second memory cells in the memory device and located over the first deck of memory cells, the second deck including a second channel structure extending through the second memory cells;
a third deck of third memory cells in the memory device and located over the second deck of memory cells;
a first interface between the first and second decks, the first interface including a first undoped polysilicon structure between and contacting the first and second channel structures;
a second interface between the second and third decks, the second interface including a second undoped poly silicon structure between and contacting the second and third channel structures;
a first level of polysilicon structure between the first and second decks and separated from the first undoped polysilicon structure by a first dielectric structure; and
a second level of polysilicon structure between the second and third decks and separated from the second undoped poly silicon structure by a second dielectric structure.

18. The apparatus of claim 17 , wherein:
the first level of poly silicon structure includes conductively doped poly silicon; and
the second level of polysilicon structure includes conductively doped polysilicon.

19. The apparatus of claim 17 , further comprising:
a first additional level of poly silicon structure between the first and second decks and separated from the first undoped polysilicon structure; and
a second additional level of poly silicon structure between the second and third decks and separated from the second undoped polysilicon structure.

20. The apparatus of claim 19 , wherein:
the first level of poly silicon structure is electrically coupled to first additional level of polysilicon structure; and
the second level of polysilicon structure is electrically coupled to second additional level of poly silicon structure.

Assignees

• Micron Technology Inc

Inventors

• Li Benben
• Goda Akira
• Abdelrahaman Ramey M
• Laboriante Ian C
• Parat Krishna K

Classifications

• G11C11/409 Primary

  Read-write [R-W] circuits · CPC title

• H10B41/35 Primary

  with a cell select transistor, e.g. NAND · CPC title

• G11C16/0475 Primary

  comprising two or more independent storage sites which store independent data · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title