Apparatuses and methods for forming multiple decks of memory cells

Patent metadata

Field	Value
Publication number	US-9362300-B2
Application number	US-201414509621-A
Country	US
Kind code	B2
Filing date	Oct 8, 2014
Priority date	Oct 8, 2014
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

First claim

What is claimed is:

1. An apparatus comprising:
first memory cells located in different levels in a first portion of the apparatus;
second memory cells located in different levels in a second portion of the apparatus;
a switch located in one of the first and second portions and between the first and second memory cells;
first control gates located in the first portion to access the first memory cells;
second control gates located in the second portion to access the second memory cells; and
a third control gate to control the switch during an operation of the apparatus, the third control gate located the between the first and second control gates.

2. The apparatus of claim 1 , wherein the third control gate includes conductively doped semiconductor material of a first conductivity type, and each of the first and second control gates includes conductively doped semiconductor material of a second conductivity type.

3. The apparatus of claim 2 , wherein the first conductivity type includes a p-type conductivity, and the second conductivity type includes an n-type conductivity.

4. The apparatus of claim 1 , wherein the third control gate and each of the first and second control gates includes conductively doped semiconductor material of a same conductivity type.

5. The apparatus of claim 1 , wherein the switch and each of the first and second memory cells have different structures.

6. The apparatus of claim 1 , wherein the switch and each of the first and second memory cells have a same structure.

7. The apparatus of claim 1 , further comprising at least one additional switch located between the first and second memory cells.

8. The apparatus of claim 1 , wherein the first and second memory cells and the switch are part of a string coupled between a data line and a source.

9. A method comprising:
applying a first voltage to first control gates and second control gates of a memory device during one of an erase operation and an erase verify operation of the memory device; and
applying a second voltage greater than the first voltage to an additional control gate of the memory device during one of the erase operation and the erase verify operation, the additional control gate being located between the first control gates and the second control gates.

10. The method of claim 9 , further comprising:
applying a third voltage greater than the first voltage to a second additional control gate of the memory device during one of the erase operation and the erase verify operation, the second additional control gate being located between the first control gates and the second control gates.

11. The method of claim 9 , wherein the second and third voltages have different values.

12. The method of claim 9 , wherein the additional control gate has an insulated transistor-gate structure.

13. The method of claim 12 , wherein the insulated transistor-gate structure includes a metal-oxide-semiconductor (MOS) structure.

14. A method comprising:
applying a first voltage to first control gates and second control gates of a memory device during an operation of the memory device, each of the first and second control gates used to access memory cells associated with the first and second control gates; and
applying a second voltage to an additional control gate of the memory device during the operation, the additional control gate being located between the first control gates and the second control gates, wherein the additional control gate is not configured to access a memory cell of the memory device.

15. The method of claim 14 , wherein the additional control gate has an insulated transistor-gate structure.

16. The method of claim 15 , wherein the insulated transistor-gate structure includes a metal-oxide-semiconductor (MOS) structure.

17. The method of claim 14 , further comprising:
applying a third voltage to a second additional control gate of the memory device during the operation, the second additional control gate being located between the first control gates and the second control gates, wherein the second additional control gate is not configured to access a memory cell of the memory device.

18. The method of claim 14 , wherein the first and second voltages have different values.

19. The method of claim 14 , wherein the first and second voltages have a same value.

20. The method of claim 14 , wherein the operation includes an erase operation.

21. The method of claim 14 , wherein the operation includes an erase verify operation.

22. The method of claim 14 , wherein the operation includes a write operation.

23. The method of claim 14 , wherein the operation includes a read operation.

Assignees

• Micron Technology Inc

Inventors

• Lu Zhenyu
• Lindsay Roger W
• Goda Akira
• Hopkins John

Classifications

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/0475

  comprising two or more independent storage sites which store independent data · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title