Multi-decks memory device including inter-deck switches

Patent metadata

Field	Value
Publication number	US-11289163-B2
Application number	US-202017087166-A
Country	US
Kind code	B2
Filing date	Nov 2, 2020
Priority date	Dec 21, 2017
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

First claim

What is claimed is:

1. An apparatus comprising:
first, memory cells, each the first memory cells including a charge-storage portion;
second memory cells located over the first memory cells, each the second memory cells including a charge-storage portion;
first control gates adjacent the first memory cells;
second control gates adjacent the second memory cells;
a first channel structure extending in a direction from one memory cell to the next memory cell of the first memory cells and separated from the charge-storage portion of each of first memory cells by a first dielectric structure;
a second channel structure extending in a direction from one memory cell to the next memory cell of the second memory cells and separated from the charge-storage portion of each of second memory cells by a second dielectric structure;
an additional control gate located between the first control gates and the second control gates;
a conductive structure located between the first and second channel structures and contacting the first and second channel structures, wherein the conductive structure has a lower doping concentration than each of the first and second channel structures; and
an addition dielectric structure between the additional control gate and the conductive structure, the additional dielectric structure contacting the conductive structure and the additional control gate.

2. The apparatus of claim 1 , wherein the first and second channel structures have a same doping concentration.

3. An apparatus comprising;
first memory cells, each the first memory cells including a charge-storage portion;
second memory cells located over the first memory cells, each the second memory cells including a charge-storage portion;
first control gates adjacent the first memory cells;
second control gates adjacent the second memory cells;
a first channel structure extending in a direction from one memory cell to the next memory cell of the first memory cells and separated from the charge-storage portion of each of first memory cells by a first dielectric structure;
a second channel structure extending in a direction from one memory cell to the next memory cell of the second memory cells and separated from the charge-storage portion of each of second memory cells by a second dielectric structure;
an additional control gate located between the first control gates and the second control gates;
a conductive structure located between the first and second channel structures and contacting the first and second channel structures; and
an addition dielectric structure between the additional control gate and the conductive structure, the additional dielectric structure contacting the conductive structure and the additional control gate, wherein the conductive structure includes N− doped polysilicon.

4. The apparatus of claim 1 , wherein the additional control gate and each of the first and second control gates include a same conductivity type.

5. The apparatus of claim 1 , wherein each of the first and second control gates and the additional control gate have a same thickness.

6. The apparatus of claim 1 , wherein each of the first and second control gates and the additional control gate have different thicknesses.

7. The apparatus of claim 1 , further comprising:
a second additional control gate located between the first control gates and the second control gates, wherein the conductive structure contacts the additional dielectric structure and the second additional control gate.

8. The apparatus of claim 7 , wherein the additional control gate and the second additional control gate are electrically coupled to each other.

9. An apparatus comprising:
first conductor materials and first dielectric materials interleaved with the first conductor materials in a memory device;
second conductor materials and second dielectric materials interleaved with the second conductor materials in the memory device, the second conductor materials and the second dielectric materials located over the first conductor materials and the first dielectric materials;
a first polysilicon structure extending through the first conductor materials and the first dielectric materials and electrically separated from the first conductive materials;
a second polysilicon structure extending through the second conductor materials and the second dielectric materials and electrically separated from the second conductive materials;
an additional polysilicon structure between and contacting the first and second polysilicon structures, wherein the additional polysilicon structure has a same conductivity type as the contacting the first and second polvsilicon structures; and
a level of polysilicon between the first and second conductor materials, the level of polysilicon being separated from the additional polysilicon structure by a dielectric structure.

10. The apparatus of claim 9 , wherein the level of polysilicon has a same conductivity type as the first and second conductor materials.

11. The apparatus of claim 9 , wherein the level of polysilicon has a thickness greater than a thickness of each of the first and second conductor materials.

12. The apparatus of claim 9 , wherein each of the first and second polysilicon structures has a doping concentration different from a doping concentration of the additional polysilicon structure.

13. The apparatus of claim 9 , wherein each of the first and second polysilicon structures is doped polysilicon, and the additional polysilicon structure is undoped polysilicon.

14. The apparatus of claim 9 , further comprising:
an additional level of polysilicon between the first and second conductor materials, the additional level of polysilicon being separated from the additional polysilicon structure by the dielectric structure, wherein the level of polysilicon and the additional level of polysilicon are part of respective control gates of respective switches between the first conductor materials and the second conductor materials.

15. An apparatus comprising: a first deck of first memory cells in a memory device, the first deck including a first channel structure extending through the first memory cells; a second deck of second memory cells in the memory device and located over the first deck of memory cells, the second deck including a second channel structure extending through the second memory cells; a third deck of third memory cells in the memory device and located over the second deck of memory cells; a first interface between the first and second decks, the first interface including a first polysilicon structure between and contacting the first and second channel structures; a second interface between the second and third decks, the second interface including a second polysilicon structure between and contacting the second and third channel structures; a first level of polysilicon structure between the first and second decks and separated from the first polysilicon structure by a first dielectric structure; and a second level of polysilicon structure between the second and third decks and separated from the second polysilicon structure by a second dielectric structure, wherein at least one of the first and second polysilicon structures includes N− doped polysilicon.

Assignees

• Micron Technology Inc

Inventors

• Li Benben
• Goda Akira
• Abdelrahaman Ramey M
• Laboriante Ian C
• Parat Krishna K

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/0475 Primary

  comprising two or more independent storage sites which store independent data · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• H01L27/2481

  Electricity · mapped topic