Method of room temperature covalent bonding

Patent metadata

Field	Value
Publication number	US-11760059-B2
Application number	US-201916521493-A
Country	US
Kind code	B2
Filing date	Jul 24, 2019
Priority date	May 19, 2003
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH 2 species. This may be accomplished by exposing the bonding layer to an NH 4 OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

First claim

The invention claimed is:

1. A bonded structure comprising:
a first semiconductor element;
a first bonding layer disposed on the first semiconductor element, the first bonding layer comprising a first oxide layer comprising fluorine and a second oxide layer comprising fluorine deposited directly on the first oxide layer to define an interface between the first oxide layer and the second oxide layer, the first oxide layer separate from the second oxide layer, wherein the first oxide layer and the second oxide layer are planarized;
a second semiconductor element; and
a second bonding layer disposed on the second semiconductor element,
wherein the second oxide layer and the second bonding layer are directly bonded to one another.

2. The bonded structure of claim 1 , further comprising a fluorine concentration within the first bonding layer having a first peak at an interface between the first and second bonding layers and a second peak at the interface between the first and second oxide layers.

3. The bonded structure of claim 1 , wherein the second bonding layer comprises a third oxide layer on the second semiconductor element and a fourth oxide layer on the third oxide layer.

4. The bonded structure of claim 1 , wherein the second oxide layer is disposed directly on the first oxide layer without intervening layers.

5. The bonded structure of claim 1 , wherein the second oxide layer is planarized to a level sufficient for direct bonding with the second bonding layer.

6. The bonded structure of claim 1 , wherein the second oxide layer is polished to have a surface roughness of 1 Å to 3 Å.

7. The bonded structure of claim 1 , wherein the first bonding layer comprises a surface SiOF layer.

8. The bonded structure of claim 1 , further comprising a nitrogen species at an interface between the first and second bonding layers.

9. The bonded structure of claim 8 , further comprising Si—N covalent bonds at the interface between the first and second bonding layers.

Assignees

• Invensas Bonding Tech Inc
• Adeia Semiconductor Bonding Technologies Inc

Inventors

• Tong Qin-Yi

Classifications

• H10W72/072

  of bump connectors · CPC title

• H10W72/29

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• H10W72/30

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• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/07331

  Connecting techniques · CPC title