Multilayer ceramic electronic package with modulated mesh topology and alternating rods

Patent metadata

Field	Value
Publication number	US-11071197-B2
Application number	US-201816137633-A
Country	US
Kind code	B2
Filing date	Sep 21, 2018
Priority date	Sep 21, 2018
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

An electronic package including modulated mesh planes can reduce crosstalk between adjacent signal wires. Modulated mesh planes above and below a wiring plane include sets of adjacent wires arranged parallel to signal wires within the wiring plane, and sets of adjacent wires arranged perpendicular to the signal wires. The wires in each of the mesh planes are electrically interconnected and insulated from the signal wires by a dielectric layer. The electronic package also includes a region of the mesh planes having the adjacent wires that are perpendicular to the signal wires separated by a first distance, and another region of the mesh planes having adjacent wires perpendicular to the signal wires separated by a distance greater than the first distance. A set of rectangular mesh areas of the mesh planes can be populated with supplemental wires and via interconnect structures which can further reduce crosstalk.

First claim

What is claimed is:

1. An electronic package including modulated mesh planes with supplemental wires and via interconnect structures for reducing signal crosstalk between adjacent signal wires within the electronic package, the electronic package comprising:
a wiring plane located in a parallel planar orientation between an upper mesh plane and a lower mesh plane, the wiring plane including a set of adjacent signal wires, each signal wire of the set of adjacent signal wires extending parallel to a first axis and electrically insulated by a dielectric layer;
the upper mesh plane that includes:
a first set of wires, each wire of the first set of wires extending parallel to the first axis; and
a second set of wires, each wire of the second set of wires:
extending parallel to a second axis that is orthogonal to the first axis;
intersecting with and electrically interconnected to the first set of wires; and
electrically insulated from the wiring plane by a dielectric layer; and

the lower mesh plane that includes:
a third set of wires, each wire of the third set of wires extending parallel to the first axis; and
a fourth set of wires, each wire of the fourth set of wires:
extending parallel to the second axis;
intersecting with and electrically interconnected to the third set of wires; and
electrically insulated from the wiring plane by a dielectric layer; and

a first region of the upper and lower mesh planes, wherein adjacent wires of the second set of wires are separated by a first distance and corresponding adjacent wires of the fourth set of wires are separated by the first distance;
a second region of the upper and lower mesh planes, wherein adjacent wires of the second set of wires are separated by a second distance that is greater than the first distance and corresponding adjacent wires of the fourth set of wires are separated by the second distance;
a set of mesh areas of the upper and lower mesh planes, the mesh areas having rectangular perimeters including portions of adjacent wires of the first set of wires that intersect with portions of adjacent wires of the second set of wires;
a set of supplemental wires, each wire of the set of supplemental wires located within a first portion of the set of mesh areas and configured to electrically connect adjacent wires of the second set of wires;
a set of vias located within a second portion of the set of mesh areas; and
a set of via interconnect structures, each via interconnect structure of the set of via interconnect structures located within the second portion of the set of mesh areas and configured to electrically connect the set of vias to adjacent wires of the first set of wires and to adjacent wires of the second set of wires.

2. The electronic package of claim 1 , wherein the set of supplemental wires and the set of via interconnect structures are arranged in a pattern that alternates along both a direction of the first axis and a direction of the second axis.

3. The electronic package of claim 1 , wherein supplemental wires located within the second region of the upper and lower mesh planes are longer than the supplemental wires located within the first region of the upper and lower mesh planes.

4. The electronic package of claim 1 , wherein each via interconnect structure of the set of via interconnect structures includes a first interconnect wire that electrically interconnects adjacent wires of the first set of wires to the corresponding via and that further includes a second interconnect wire that electrically interconnects adjacent wires of the second set of wires to the corresponding via.

5. The electronic package of claim 1 , wherein the dielectric layer includes a glass-ceramic material.

6. The electronic package of claim 1 , wherein the electronic package is selected from the group consisting of: a single-chip module (SCM), and a multi-chip module (MCM).

7. The electronic package of claim 1 , wherein a width of the signal wires is less than 60 μm.

8. The electronic package of claim 1 , wherein a thickness of the signal wires is less than 15 μm.

9. The electronic package of claim 1 , wherein a ratio of the second distance to the first distance is in a range between 2 and 3.

10. An electronic system for reducing signal crosstalk between adjacent signal wires within an electronic package, the electronic system comprising:
the electronic package, electrically and mechanically connected to a printed circuit board (PCB), the electronic package including:
a wiring plane located in a parallel planar orientation between an upper mesh plane and a lower mesh plane, the wiring plane including a set of adjacent signal wires, each signal wire of the set of adjacent signal wires extending parallel to a first axis and electrically insulated by a dielectric layer;
the upper mesh plane that includes:
a first set of wires, each wire of the first set of wires extending parallel to the first axis; and
a second set of wires, each wire of the second set of wires:
extending parallel to a second axis that is orthogonal to the first axis;
intersecting with and electrically interconnected to the first set of wires; and
electrically insulated from the wiring plane by a dielectric layer; and

the lower mesh plane that includes:
a third set of wires, each wire of the third set of wires extending parallel to the first axis; and
a fourth set of wires, each wire of the fourth set of wires:
extending parallel to the second axis;
intersecting with and electrically interconnected to the third set of wires; and
electrically insulated from the wiring plane by a dielectric layer; and

a first region of the upper and lower mesh planes, wherein adjacent wires of the second set of wires are separated by a first distance and corresponding adjacent wires of the fourth set of wires are separated by the first distance;
a second region of the upper and lower mesh planes, wherein adjacent wires of the second set of wires are separated by a second distance that is greater than the first distance and corresponding adjacent wires of the fourth set of wires are separated by the second distance;
a set of mesh areas of the upper and lower mesh planes, the mesh areas having rectangular perimeters including portions of adjacent wires of the first set of wires that intersect with portions of adjacent wires of the second set of wires;
a set of supplemental wires, each wire of the set of supplemental wires located within a first portion of the set of mesh areas and configured to electrically connect adjacent wires of the second set of wires; and
a set of via interconnect structures, each via interconnect structure of the set of via interconnect structures located within a second portion of the set of mesh areas and configured to electrically connect vias to adjacent wires of the first set of wires and to adjacent wires of the first set of wires;
an integrated circuit (IC) electrically and mechanically connected to the electronic package; and
the PCB.

11. The electronic system of claim 10 , wherein each via interconnect structure includes a first interconnect wire that electrically interconnects adjacent wires of the first set of wires to the via and that further includes a second interconnect wire that electrically interconnects adjacent wires of the second set of wires to the via.

12. The electronic system of claim 10 , wherein the dielectric layer includes a glass-ceramic material.

13. The electronic system of claim 10 , wherein a width of the signal wires is less than 60 μm.

14. The electronic system of claim 10 , wherein a thickness of the signal wires is less than 15 μm.

Assignees

• IBM

Inventors

• Choi Jinwoo
• Dreps Daniel M
• Zhang Yanyan

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W44/209

  Vertical interconnections, e.g. vias · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title