Integrated circuit including asymmetric power line and method of designing the same

Patent metadata

Field	Value
Publication number	US-11755809-B2
Application number	US-202117458948-A
Country	US
Kind code	B2
Filing date	Aug 27, 2021
Priority date	Oct 13, 2020
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

An integrated circuit is provided. The integrated circuit includes a first cell that has a first height and is arranged in a first row which extends in a first direction; a second cell that has a second height and is arranged in a second row which extends in the first direction and is adjacent to the first row, wherein the second cell is adjacent to the first cell in a second direction perpendicular to the first direction; and a power line that extends in the first direction, is arranged on a boundary between the first cell and the second cell, and is configured to supply power to the first cell and the second cell. The first cell overlaps a first width of the power line along the second direction and the second cell overlaps a second width of the power line along the second direction, and the first width and the second width are different from each other.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first cell that has a first height and is arranged in a first row which extends in a first direction;
a second cell that has a second height and is arranged in a second row which extends in the first direction and is adjacent to the first row, wherein the second cell is adjacent to the first cell in a second direction perpendicular to the first direction; and
a power line that extends in the first direction, is arranged on a boundary between the first cell and the second cell, and is configured to supply power to the first cell and the second cell,
wherein the first cell overlaps a first width of the power line along the second direction and the second cell overlaps a second width of the power line along the second direction, and
wherein the first width and the second width are different from each other.

2. The integrated circuit of claim 1 , wherein the first height is greater than the second height, and the first width is greater than the second width.

3. The integrated circuit of claim 1 , wherein the first cell comprises at least one first conductive pattern formed in a first wiring layer and arranged on a plurality of first tracks which extend in the first direction,
wherein the second cell comprises at least one second conductive pattern formed in the first wiring layer and arranged on a plurality of second tracks which extend in the first direction,
wherein a first quantity of the plurality of first tracks is greater than a second quantity of the plurality of second tracks, and
wherein the first width is greater than the second width.

4. The integrated circuit of claim 3 , wherein an interval between the plurality of first tracks is a first interval,
wherein an interval between the plurality of second tracks is a second interval,
wherein an interval between the power line and a first adjacent track closest to the power line from among the plurality of first tracks is greater than the first interval, and
wherein an interval between the power line and a second adjacent track closest to the power line from among the plurality of second tracks is greater than the second interval.

5. The integrated circuit of claim 3 , wherein the power line is arranged on the first wiring layer,
wherein the integrated circuit further comprises an upper power line which is connected to the power line, extends in the first direction, and is arranged on a third wiring layer,
wherein the third wiring layer is arranged on the first wiring layer, and
wherein a width of the upper power line is asymmetric based on the boundary.

6. The integrated circuit of claim 1 , wherein the first cell comprises a plurality of first gate electrodes which extend in the second direction,
wherein the second cell comprises a plurality of second gate electrodes which extend in the second direction, and
wherein a first pitch between the plurality of first gate electrodes corresponds to a second pitch between the plurality of second gate electrodes.

7. The integrated circuit of claim 6 , wherein a cutting region is arranged below the power line between the plurality of first gate electrodes and the plurality of second gate electrodes, and
wherein a center of the cutting region passes through by the boundary.

8. The integrated circuit of claim 6 , wherein the first cell comprises a plurality of first active patterns which extend in the first direction and connect to at least one of the plurality of first gate electrodes to form a transistor,
wherein the second cell comprises a plurality of second active patterns which extend in the first direction and connect to at least one of the plurality of second gate electrodes,
wherein a first quantity of the plurality of first active patterns is greater than a second quantity of the plurality of second active patterns, and
wherein the first width is greater than the second width.

9. The integrated circuit of claim 1 , further comprising a dummy pattern which extends in the first direction below the power line, and
wherein the boundary is located along the dummy pattern.

10. The integrated circuit of claim 1 , further comprising a via connected to the power line in a vertical direction and electrically connected to the power line, the first cell and the second cell,
wherein a center of the via passes through by the boundary in the first direction.

11. The integrated circuit of claim 1 , further comprising:
a plurality of first cells, each of which has the first height and is arranged on M first rows adjacent to each other, wherein M is a natural number; and
a plurality of second cells, each of which as the second height and is arranged on N second rows adjacent to each other, wherein N is a natural number,
wherein the first cell is one of the plurality of first cells, and
wherein the second cell is one of the plurality of second cells.

12. An integrated circuit comprising:
a first cell that is arranged on a first row, wherein the first row extends in a first direction and has a first height;
a second cell that is arranged on a second row, wherein the second row is adjacent to the first row and has the first height;
a third cell that is arranged on a third row, wherein the third row is adjacent to the second row and has a second height;
a first power line arranged on a first boundary where the first row and the second row contact each other, wherein the first power line is configured to provide power to the first cell and the second cell; and
a second power line arranged on a second boundary where the second row and the third row contact each other, wherein the second power line is configured to provide power to the second cell and the third cell,
wherein the first power line is symmetric based on the first boundary, and
wherein the second power line is asymmetric based on the second boundary.

13. The integrated circuit of claim 12 , wherein the first cell overlaps a first width of the first power line and the second cell overlaps a second width of the first power line,
wherein the second cell overlaps a third width of the second power line and the third cell overlaps a fourth width of the second power line,
wherein the first width, the second width and the third width have a common value, and
wherein the fourth width is different from the common value.

14. The integrated circuit of claim 13 , wherein the first height is greater than the second height, and
wherein the common value is greater than the fourth width.

15. The integrated circuit of claim 13 , wherein each of the first cell and the second cell comprises at least one first conductive pattern arranged on a plurality of first tracks which extend in the first direction and are spaced apart from each other at a first track interval,
wherein the third cell comprises at least one second conductive pattern arranged on a plurality of second tracks which extend in the first direction and are spaced apart from each other at a second track interval,
wherein when a first quantity of the plurality of first tracks is greater than a second quantity of the plurality of second tracks, the common value is greater than the fourth width, and
wherein when the second quantity is greater than the first quantity, the fourth width is greater than the common value.

16. The integrated circuit of claim 13 , wherein the first cell, the second cell and the third cell respectively comprise a plurality of first gate electrodes, a plurality of second gate electrodes and a plurality of third gate electrodes,
wherein the plurality of first gate electrode

Assignees

• Samsung Electronics Co Ltd

Inventors

• YU Jisu
• Seo Jaewoo
• You Hyeongyu
• Baek Sanghoon
• Jung Jonghoon

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/427 Primary

  Power or ground buses · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title