Dynamic core selection for heterogeneous multi-core systems

Patent metadata

Field	Value
Publication number	US-11755099-B2
Application number	US-202217852066-A
Country	US
Kind code	B2
Filing date	Jun 28, 2022
Priority date	Mar 11, 2011
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

Example methods and apparatus to facilitate dynamic core selection are disclosed. An example apparatus includes a first processor core of a first type; a second processor core of a second type different from the first type; and software to: access a user-supplied hint indicative of a user preference to execute program code on the first processor core, the user-supplied hint including a user-defined attribute of the program code; monitor performance of the program code on the first processor core; determine, based on the user-defined attribute of the program code, a predicted performance of the program code on the second processor core is better than the performance of the program code on the first processor core; and ignore the user preference by migrating the program code from the first processor core for execution on the second processor core.

First claim

The invention claimed is:

1. A multi-core computer system comprising:
a first processor core of a first type;
a second processor core of a second type different from the first type; and
software to:
access a user-supplied hint indicative of a user preference to execute program code on the first processor core, the user-supplied hint including a user-defined attribute of the program code;
monitor performance of the program code on the first processor core;
determine, based on the user-defined attribute of the program code, a predicted performance of the program code on the second processor core is better than the performance of the program code on the first processor core; and
ignore the user preference by migrating the program code from the first processor core for execution on the second processor core.

2. The multi-core computer system of claim 1 , wherein the software is to determine the predicted performance of the program code on the second processor core is better than the performance of the program code on the first processor core by profiling the program code to generate the user-supplied hint.

3. The multi-core computer system of claim 1 , wherein the software is further to:
monitor, subsequent to the migration of execution of the program code to the second processor core, performance of the execution of the program code by the second processor core;
determine, based on the performance of execution of the program code on the second processor core and the user-supplied hint, whether the performance of the program code by the first processor core is better than the performance of the program code on the second processor core; and
migrate execution of the program code from the second processor core back to the first processor core in response to a determination that the performance of the program code on the first processor core is better than the performance of the program code on the second processor core.

4. The multi-core computer system of claim 1 , wherein the first processor core is an in-order processor core and the second processor core is an out-of-order processor core.

5. The multi-core computer system of claim 1 , wherein the second processor core is an in-order processor core and the first processor core is an out-of-order processor core.

6. The multi-core computer system of claim 1 , wherein the software is further to power up the second processor core in response to the determination that the predicted performance of the program code on the second processor core is better than the monitored performance of the program code on the first processor core.

7. The multi-core computer system of claim 1 , wherein the software is further to power down the first processor core in response to the migration of execution of the program code from the first processor core to the second processor core.

8. At least one computer readable storage disk or storage device comprising instructions which, when executed, cause one or more processors to at least:
access a user-supplied hint indicative of a user preference to execute program code on a first processor core of a first type, the user-supplied hint including a user-defined attribute of the program code;
monitor performance of the program code on the first processor core;
determine, based on the user-defined attribute of the program code, a predicted performance of the program code on a second processor core is better than the performance of the program code on the first processor core, the second processor core of a second type different than the first type; and
ignore the user preference by migrating the program code from the first processor core for execution on the second processor core.

9. The at least one computer readable storage disk or storage device of claim 8 , wherein the instructions cause the one or more processors to determine the predicted performance of the program code on the second processor core is better than the performance of the program code on the first processor core by profiling the program code to generate the user-supplied hint.

10. The at least one computer readable storage disk or storage device of claim 8 , wherein the instructions cause the one or more processors to:
monitor, subsequent to the migration of execution of the program code to the second processor core, performance of the execution of the program code by the second processor core;
determine, based on the performance of execution of the program code on the second processor core and the user-supplied hint, whether the performance of the program code by the first processor core is better than the performance of the program code on the second processor core; and
migrate execution of the program code from the second processor core back to the first processor core in response to a determination that the performance of the program code on the first processor core is better than the performance of the program code on the second processor core.

11. The at least one computer readable storage disk or storage device of claim 8 , wherein the first processor core is an in-order processor core and the second processor core is an out-of-order processor core.

12. The at least one computer readable storage disk or storage device of claim 8 , wherein the second processor core is an in-order processor core and the first processor core is an out-of-order processor core.

13. The at least one computer readable storage disk or storage device of claim 8 , wherein the instructions cause the one or more processors to power up the second processor core in response to the determination that the predicted performance of the program code on the second processor core is better than the monitored performance of the program code on the first processor core.

14. The at least one computer readable storage disk or storage device of claim 8 , wherein the instructions cause the one or more processors to power down the first processor core in response to the migration of execution of the program code from the first processor core to the second processor core.

15. An apparatus comprising:
a first processor core of a first type;
a second processor core of a second type different from the first type;
instructions; and
processor circuitry to execute the instructions to:
access a user-supplied hint indicative of a user preference to execute program code on the first processor core of the first type, the user-supplied hint including a user-defined attribute of the program code;
monitor a first performance of the program code on the first processor core;
predict a second performance of the program code on the second processor core;
determine, based on the user-defined attribute of the program code, that the second performance of the program code on the second processor core is better than the first performance of the program code on the first processor core; and
ignore the user preference by migrating the program code from the first processor core for execution on the second processor core.

16. The apparatus of claim 15 , wherein the processor circuitry is to determine the second performance of the program code on the second processor core is better than the first performance of the program code on the first processor core by profiling the program code to generate the user-supplied hint.

17. The apparatus of claim 15 , wherein the processor circuitry is further to:
monitor, subsequent to the migration of execution of the program code to the second processor core, third performance of the execution of the program code by the second processor core;

Assignees

• Intel Corp

Inventors

• Wu Youfeng
• Hu Shiliang
• Borin Edson
• Wang Cheng

Classifications

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title

• Y02D30/50

  in wire-line communication networks, e.g. low power modes or reduced link rate · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F2209/501

  Performance criteria · CPC title

• G06F2201/88

  Monitoring involving counting · CPC title