Dynamic core selection for heterogeneous multi-core systems

Patent metadata

Field	Value
Publication number	US-9501135-B2
Application number	US-201414169955-A
Country	US
Kind code	B2
Filing date	Jan 31, 2014
Priority date	Mar 11, 2011
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

First claim

What is claimed is:

1. One or more non-transitory computer-readable storage media comprising a plurality of instructions stored thereon that, in response to execution, cause a processing system to:
execute program code on a first processor core of the processing system, wherein the first processor core is of a first type;
monitor performance and collect statistics of the first processor core executing the program code;
predict, while the program code is executed by the first processor core, performance of executing the program code on a second processor core of the processing system based at least in part on the monitored performance and collected statistics of the first processor core executing the program code, wherein the second processor core is of a second type, different than the first type; and
switch execution of the program code from the first processor core to the second processor core in response to a determination that the predicted performance of executing the program code on the second processor core is better than the performance of the first processor core executing the program code.

2. The one or more non-transitory computer-readable storage media of claim 1 , wherein the plurality of instructions further cause the processing system to power up the second processor core from a low power state in response to the determination that the predicted performance of executing the program code on the second processor core is better than the performance of the first processor core executing the program code.

3. The one or more non-transitory computer-readable storage media of claim 1 , wherein the plurality of instructions further cause the processing system to power down the first processor core to a low power state in response to the determination that the predicted performance of executing the program code on the second processor core is better than the performance of the first processor core executing the program code.

4. The one or more non-transitory computer-readable storage media of claim 1 , wherein the first processor core comprises an out-of-order processor core and the second processor core comprises an in-order processor core.

5. The one or more non-transitory computer-readable storage media of claim 1 , wherein the second processor core comprises an out-of-order processor core and the first processor core comprises an in-order processor core.

6. The one or more non-transitory computer-readable storage media of claim 1 , wherein to predict the performance of the second processor core comprises to:
execute a plurality of code segments on both the first processor core and the second processor core,
collect the respective performance information and statistics of the first and second processor cores while executing the code segments, and
determine a best fit function F such that differences between F (performance information and statistics of the first core) and the performance of the second processing core are minimized.

7. The one or more non-transitory computer-readable storage media of claim 1 , wherein to collect statistics of the first processor core executing the program code comprises to collect statistics indicative of a branch miss rate or a cache miss rate of the first processor core.

8. The one or more non-transitory computer-readable storage media of claim 7 , wherein to switch execution of the program code from the first processor core to the second processor core comprises to switch execution of the program code from the first processor core to an out-of-order processor core in response to a determination that the branch miss rate or the cache miss rate is greater than a threshold rate.

9. The one or more non-transitory computer-readable storage media of claim 7 , wherein to switch execution of the program code from the first processor core to the second processor core comprises to switch execution of the program code from the first processor core to an in-order processor core in response to a determination that the branch miss rate or the cache miss rate is less than a threshold rate.

10. One or more non-transitory computer-readable storage media comprising a plurality of instructions stored thereon that, in response to execution, cause a processing system to:
execute program code on a first processor core of the processing system for a first number of cycles, wherein the first processor core is of a first type;
signal power up of a second processor core of the processing system, wherein the second processor core is of a second type, different than the first type; and
collect a first performance metric of the first processor core executing the program code for a second number of cycles, and
in response to a determination that the first performance metric is better than a previously determined core performance metric, signal power down of the second processor core prior to execution of the program code on the second processing core after the second processing core has powered up and continue execution of the program code on the first processor core; or
in response to a determination that the first performance metric is not better than the previously determined core performance metric, switch execution of the program code from the first processor core to the second processor core and collect a second performance metric of the second processor core executing the program code for the second number of cycles.

11. The one or more non-transitory computer-readable storage media of claim 10 , wherein the plurality of instructions further cause the processing system, in response to a determination that the second performance metric is not better than the first performance metric, to switch execution of the program code from the second processor core back to the first processor core and signal power down of the second processor core.

12. The one or more non-transitory computer-readable storage media of claim 10 , wherein the plurality of instructions further cause the processing system, in response to a determination that the second performance metric is better than the first performance metric, signal power down of the first processing core and set the previously determined core performance metric to an average of the first performance metric and the second performance metric.

13. The one or more non-transitory computer-readable storage media of claim 10 , wherein to signal power up of the second processor core comprises to signal power up a third number of cycles before the end of the sum of the first number of cycles and the second number of cycles.

14. The one or more non-transitory computer-readable storage media of claim 10 , wherein the plurality of instructions further cause the processing system to set the previously determined core performance metric to the previously determined core performance metric multiplied by an inflation factor in response to a determination that the first performance metric is better than the previously determined core performance metric.

15. The one or more non-transitory computer-readable storage media of claim 10 , wherein the plurality of instructions further cause the processing system to force a switch of execution of the program code from the first processor core to the second processor core and collect a second performance metric of the second processor core executing the program code for the second number of cycles, at least once for every K comparisons of the first performance metric and the previously determined core performance metric, wherein K is a natural number.

16. The one or more non-transitory computer-readable storage media

Assignees

• Intel Corp

Inventors

• Wu Youfeng
• Hu Shiliang
• Borin Edson
• Wang Cheng

Classifications

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• G06F11/3466

  Performance evaluation by tracing or monitoring · CPC title

• G06F9/5027

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• G06F9/5094

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F9/4893 Primary

  taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title