Cladded metal interconnects

Patent metadata

Field	Value
Publication number	US-11749560-B2
Application number	US-201816141522-A
Country	US
Kind code	B2
Filing date	Sep 25, 2018
Priority date	Sep 25, 2018
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.

First claim

What is claimed is:

1. An integrated circuit device comprising:
an interlayer dielectric (ILD) layer having an interconnect trench therein, the interconnect trench having sidewalls and a bottom;
a first layer on the sidewalls and the bottom of the interconnect trench;
a second layer on the first layer, the second layer including an adhesion layer material, wherein the second layer material includes at least one of osmium (Os), gold (Au), platinum (Pt), palladium (Pd), iridium (Ir), silver (Ag), and rhodium (Rh);
a metal interconnect core on the second layer in the interconnect trench, wherein the second layer clads the metal interconnect core in the interconnect trench; and
a cap on a top surface of the metal interconnect core, the cap including a cap material, wherein the cap material is the same as the second layer material, wherein the cap has a bottommost surface below an uppermost surface of the ILD layer, the bottommost surface of the cap below an uppermost surface of the first layer, and wherein the cap is over an uppermost surface of the second layer.

2. The integrated circuit device of claim 1 , wherein the metal interconnect core includes copper (Cu).

3. The integrated circuit device of claim 1 , wherein the second layer has a thickness in a range of 1 nm to 3 nm.

4. The integrated circuit device of claim 1 , wherein a thickness of the second layer is uniform, such that a thinnest part of the second layer is within 5% of a thickest part of the second layer.

5. The integrated circuit device of claim 1 , wherein the first layer provides a diffusion barrier material that prevents the metal interconnect core from diffusing into the ILD layer.

6. The integrated circuit device of claim 1 , wherein the second layer provides for formation of a conformal seed layer.

7. The integrated circuit device of claim 1 , wherein the second layer reduces metal diffusion along the interface between the metal interconnect core and the second layer.

8. The integrated circuit device of claim 1 , wherein the second layer is a bilayer structure including a third layer and a fourth layer.

9. The integrated circuit device of claim 8 , wherein the third layer has a thickness in a range of 1 nm to 3 nm.

10. The integrated circuit device of claim 8 , wherein the fourth layer has a thickness in a range of 1 nm to 3 nm.

11. The integrated circuit device of claim 8 , wherein a thickness of the third layer and a thickness of the fourth layer are uniform, such that a thinnest part of each layer is within 5% of a thickest part of each layer.

12. An integrated circuit device comprising:
an interlayer dielectric (ILD) layer having an interconnect trench therein, the interconnect trench having sidewalls and a bottom;
a first layer on the sidewalls and the bottom of the interconnect trench;
a second layer on the first layer, the second layer including an adhesion layer material; wherein the second layer material includes at least one of osmium (Os), gold (Au), platinum (Pt), palladium (Pd), iridium (Ir), silver (Ag), and rhodium (Rh);
a copper (Cu) interconnect core on the second layer in the interconnect trench, wherein the second layer dads the Cu interconnect core in the interconnect trench; and
a cap on a top surface of the Cu interconnect core, the cap including a cap material, wherein the cap material is the same as the second layer material, thereby cladding the top surface of the Cu interconnect core with the second layer material, wherein the cap has a bottommost surface below an uppermost surface of the ILD layer, the bottommost surface of the cap below an uppermost surface of the first layer, and wherein the cap is over an uppermost surface of the second layer.

13. The integrated circuit device of claim 12 , wherein the second layer has a thickness in a range of 1 nm to 3 nm.

14. The integrated circuit device of claim 12 , wherein the second layer provides for formation of a conformal Cu seed layer.

15. The integrated circuit device of claim 12 , wherein the second layer reduces Cu diffusion along the interface between the Cu interconnect core and the second layer.

16. The integrated circuit device of claim 12 , wherein the second layer is a bilayer structure including a third layer and a fourth layer.

17. The integrated circuit device of claim 16 , wherein a thickness of the third layer and a thickness of the fourth layer are uniform, such that a thinnest part of each layer is within 5% of a thickest part of each layer.

18. A method for forming a cladded metal interconnect structure, the method comprising:
forming an interlayer dielectric (ILD) layer having an interconnect trench therein, the interconnect trench having sidewalls and a bottom;
conformally depositing a conformal first layer on the sidewalls and the bottom of the interconnect trench;
selectively depositing a second layer on the conformal first layer, the second layer including an adhesion layer material, wherein the second layer material includes at least one of osmium (Os), gold (Au), platinum (Pt), palladium (Pd), iridium (Ir), silver (Ag), and rhodium (Rh);
depositing an interconnect metal in the interconnect trench such that the second layer dads the interconnect metal in the interconnect trench; and
selectively depositing a cap on a top surface of the interconnect metal, the cap including a cap material, wherein the cap material is the same as the second layer material, wherein the cap has a bottommost surface below an uppermost surface of the ILD layer, the bottommost surface of the cap below an uppermost surface of the first layer, and wherein the cap is over an uppermost surface of the second layer.

19. The method of claim 18 , further comprising at least one of: depositing a seed layer onto the second layer; and recessing excess interconnect metal formed outside the trench.

Assignees

• Intel Corp

Inventors

• Marieb Thomas
• Ma Zhiyong
• Reshotko Miriam R
• Jezewski Christopher
• Griggio Flavio
• Kasim Rahim
• Toledo Nikholas G

Classifications

• H10W20/0372

  comprising multiple barrier, adhesion or liner layers · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/039

  also covering sidewalls of the conductive structures · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title