Integrated circuit with constrained metal line arrangement

Patent metadata

Field	Value
Publication number	US-11748550-B2
Application number	US-202117342006-A
Country	US
Kind code	B2
Filing date	Jun 8, 2021
Priority date	Oct 14, 2019
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

A method includes steps of dividing a first arrangement of metal lines in a circuit layout into two sets of metal lines, a first set of metal lines in a peripheral area, and a second set of metal lines in a center area. The arrangement of metal lines is configured to electrically connect to contacts of a second layer of the circuit layout. The method includes adjusting a metal line perimeter of at least one metal line in the center area to make a second arrangement of metal lines, where each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance.

First claim

What is claimed is:

1. A method of making an integrated circuit, comprising:
dividing, in a first layer of an integrated circuit layout, a first arrangement of conductive lines into a first set of conductive lines and a second set of conductive lines, wherein the first set of conductive lines is located in a peripheral area of the integrated circuit layout and the second set of conductive lines is located in a center area of the integrated circuit layout, wherein the first arrangement of conductive lines is configured to electrically connect with contacts of a second layer of the integrated circuit layout; and
adjusting a conductive line perimeter of at least one conductive line of the second set of conductive lines in the center area of the integrated circuit layout to make a second arrangement of conductive lines, wherein each adjusted conductive line perimeter is separated from the contacts in the second layer of the integrated circuit layout by at least a check distance.

2. The method of claim 1 , further comprising:
selecting a first portion of a perimeter of the at least one conductive line in the center area; and
moving the first portion of the conductive line perimeter from an initial position to a second position closer to an adjacent conductive line.

3. The method of claim 2 , wherein moving the first portion of the conductive line perimeter comprises connecting the at least one conductive line to a second conductive line.

4. The method of claim 2 , wherein moving the first portion of the conductive line perimeter comprises reducing a number of protrusions of a perimeter of the at least one conductive line.

5. The method of claim 2 , further comprising:
measuring a separation distance between the second position of the conductive line perimeter and a nearest conductive line; and
further adjusting the conductive line perimeter in response to the separation distance between the second position of the conductive line perimeter and the nearest conductive line to the second position of the conductive line perimeter being less than the check distance, wherein a check window around an adjusted segment of the at least one conductive line has a shape of the adjusted segment of the at least one conductive line at the check distance from the adjusted segment of the conductive line.

6. The method of claim 5 , further comprising extending, for a discontinuous first portion of the conductive line perimeter, at least one segment of the discontinuous first portion of the conductive line perimeter to make a first extension intersecting with a second extension or the first portion of the conductive line perimeter.

7. The method of claim 1 , further comprising:
dividing the first layer of the integrated circuit layout into a plurality of areas, wherein at least area has a top border area and a bottom border area; and
reproducing, in the top border area or the bottom border area, a third arrangement of conductive lines, wherein the third arrangement is a subset of the second set of conductive lines.

8. The method of claim 7 , wherein adjusting the conductive line perimeter of at least one conductive line in the center area of the integrated circuit layout further comprises combining at least one conductive line of the top border area or the bottom border area with one conductive line of the center area of the integrated circuit.

9. An integrated circuit, comprising, for a first area of the integrated circuit:
a set of contacts at a first layer of the integrated circuit; and
a set of conductive lines at a second layer of the integrated circuit, the second layer being over the first layer, wherein
the first area comprises a center area, a border area, a first terminal region, and a second terminal region, wherein each of the first terminal region and the second terminal region comprises,
the border area surrounds the center area on three sides,
the border area includes a top border area and a bottom border area at an opposite side of the center area from the top border area, and
conductive lines of the top border area have a repeating second pattern of conductive lines.

10. The integrated circuit of claim 9 , wherein conductive lines of the bottom border area have a third pattern of conductive lines different from the second pattern of conductive lines.

11. The integrated circuit of claim 9 , wherein the first area further comprises at least one non-terminal region between the first terminal region and the second terminal region, and the top border area of each non-terminal region has the second pattern of conductive lines.

12. The integrated circuit of claim 11 , wherein the bottom border area of each non-terminal region has a third pattern of conductive lines different from the second pattern of conductive lines.

13. A method of making an integrated circuit, comprising:
assigning, to a first set of contacts of a first layer of a first area of the integrated circuit, a first pattern of conductive lines of a second layer of the first area of the integrated circuit;
assigning, to a second set of contacts of the first layer of the first area of the integrated circuit, a second pattern of conductive lines of the second layer of the first area of the integrated circuit;
determining, for each conductive line in the second pattern of conductive lines, whether to modify a conductive line perimeter;
assigning, to a first set of conductive lines, conductive lines of the second pattern determined to not undergo modification of the conductive line perimeter;
assigning, to a second set of conductive lines, conductive lines of the second pattern determined to undergo modification of the conductive line perimeter;
modifying a conductive line perimeter of each conductive line in the second set of conductive lines to have a modified conductive line perimeter; and
generating a third pattern of conductive lines based on the first set of conductive lines, and on the second set of conductive lines, wherein the first pattern of conductive lines is in a peripheral area of the first area and the second pattern of conductive lines is in a center area of the first area.

14. The method of claim 13 , further comprising
modifying a first portion of a conductive line perimeter for a conductive line of the second area, wherein the second area is a center area of a layout of the integrated circuit, and modifying the first portion of the conductive line perimeter further comprises moving a modified portion of the conductive line perimeter to a second position at least a check distance away from a nearest conductive line to the modified portion of the conductive line perimeter.

15. The method of claim 14 , wherein modifying a first portion of the conductive line perimeter further comprises:
testing a second conductive line perimeter segment by moving the first portion of the conductive line perimeter closer to a contact of the first layer or a conductive line of the second layer;
determining whether the contact of the first layer of conductive line or the second layer is within the check distance from each edge of the second conductive line perimeter segment; and
replacing the first portion of the conductive line perimeter with the second conductive line perimeter segment in response to the second conductive line perimeter segment being beyond the check distance from a conductive line of the second layer or a contact of the first layer.

16. The method of claim 14 , wherein modifying a first portion of the conductive line perimeter further comprises connecting two conductive lines in the center area.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Tsmc China Company Ltd

Inventors

• Wang Xinyong
• Wang Qiquan
• Tien Li-Chun
• Ma Yuan

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/031 Primary

  of conductive parts of the interconnections · CPC title

• H10D84/907

  CMOS gate arrays · CPC title

• H10D84/975

  Wiring regions or routing · CPC title