Retimer application system, retimer, and data transmission method

Patent metadata

Field	Value
Publication number	US-11748294-B2
Application number	US-202117315715-A
Country	US
Kind code	B2
Filing date	May 10, 2021
Priority date	Jan 3, 2019
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

A retimer application system is provided, which includes a primary chip, a retimer, and a secondary chip. After first link training is completed, the retimer is configured to store, in a first storage area, an equalization parameter corresponding to each rate during the first link training, and data stored in the first storage area is not lost when the retimer performs a reset operation. The retimer is further configured to: receive a reset indication, and perform the reset operation according to the reset indication. The primary chip and the secondary chip are configured to perform second link training triggered by the reset indication. During the second link training, the retimer is further configured to: invoke the equalization parameter, and transparently transmit a training sequence in the second link training to the primary chip or the secondary chip based on the equalization parameter.

First claim

What is claimed is:

1. An application system, comprising:
a primary chip;
a retimer comprising a plurality of data processing circuits; and
a secondary chip, wherein the primary chip, the second chip, and the retimer participate in first link training, and, after the first link training is completed, the retimer is configured to:
store, in a first storage area, an equalization parameter corresponding to each rate during the first link training, and data stored in the first storage area is not lost when the retimer performs a reset operation;
receive a reset indication;
perform the reset operation according to the reset indication, wherein the primary chip and the secondary chip are configured to perform second link training triggered by the reset indication;
during the second link training, transparently transmit a training sequence and invoke the equalization parameter, wherein the retimer is configured to bypass the plurality of data processing circuits in the retimer while transmitting the training sequence; and
after the second link training is completed, transparently transmit service data between the primary chip and the secondary chip based on the equalization parameter.

2. The application system according to claim 1 , wherein the first storage area is a storage area in a nonvolatile memory or firmware of the retimer.

3. The application system according to claim 1 , wherein after the first link training is completed, the retimer is further configured to enter a low-delay mode.

4. The application system according to claim 3 , wherein the retimer further comprises a link state machine, and each data processing circuit of the plurality of data processing circuits is configured to convert the training sequence processed by the link state machine into serial data.

5. The application system according to claim 1 , wherein during the first link training, the retimer is further configured to:
store the equalization parameter in a register, and, after the first link training is completed,
store, in the first storage area, the equalization parameter that is stored in the register.

6. The application system according to claim 5 , wherein during the second link training, the retimer is further configured to store the equalization parameter that is stored in the first storage area in the register.

7. The application system according to claim 1 , wherein the application system further comprises a basic input/output system (BIOS), and after the first link training is completed, the BIOS is configured to send the reset indication to the retimer; or the primary chip is configured to send the reset indication to the retimer.

8. The application system according to claim 3 , wherein the retimer comprises:
a sending equalization circuit; and
a receiving equalization circuit, and after the retimer enters the low-delay mode, an output of the receiving equalization circuit is used as an input of the sending equalization circuit.

9. The application system according to claim 1 , wherein the retimer supports a plurality of protocols and is further configured to select a working protocol used by the primary chip and the secondary chip to work, and the plurality of protocols include at least one of the following: a peripheral component interconnect express (PCIe) protocol, a cache coherent interconnect for accelerators (CCIX) protocol, or a universal serial bus (USB) protocol.

10. A data transmission method, comprising:
after a primary chip, a second chip, and a retimer, wherein the retimer comprises a plurality of data processing circuits, participate in first link training, and the first link training is completed, storing, by the retimer in a first storage area, an equalization parameter corresponding to each rate during the first link training, wherein data stored in the first storage area is not lost when the retimer performs a reset operation;
receiving, by the retimer, a reset indication;
performing the reset operation according to the reset indication;
in a process in which the primary chip and the secondary chip perform second link training triggered by the reset indication,
during the second link training, transparently transmit a training sequence and invoke, by the retimer, the equalization parameter, wherein the retimer is configured to bypass the plurality of data processing circuits in the retimer while transmitting the training sequence; and
after the second link training is completed, transparently transmitting service data between the primary chip and the secondary chip based on the equalization parameter.

11. The method according to claim 10 , further comprising:
after the first link training is completed, the retimer enters a low-delay mode.

12. The method according to claim 10 , further comprising:
storing, by the retimer, the equalization parameter in a register during the first link training; and
after the first link training is completed, storing, by the retimer, the equalization parameter that is stored in the register in the first storage area.

13. The method according to claim 12 , wherein the invoking, by the retimer, of the equalization parameter comprises:
storing, by the retimer, the equalization parameter that is stored in the first storage area in the register.

14. The method according to claim 10 , further comprising:
after the first link training is completed, sending, by a basic input/output system (BIOS), the reset indication to the retimer; or,
after the first link training is completed, sending, by the primary chip, the reset indication to the retimer.

15. A retimer, comprising:
a plurality of data processing circuits;
a control circuit, wherein a primary chip, a second chip, and the retimer participate in first link training, and, after the first link training is completed, the control circuit is configured to:
store, in a first storage area, an equalization parameter corresponding to each rate during the first link training, and data stored in the first storage area is not lost after the retimer performs a reset operation;
during second link training, after the reset operation is performed, invoke the equalization parameter and bypass a plurality of data processing circuits in the retimer and transparently transmit a training sequence during the second link training, wherein the second link training is triggered by the reset operation;
after the second link training is completed, transparently transmit service data between the primary chip and the secondary chip based on the equalization parameter.

16. The retimer according to claim 15 , wherein after the first link training is completed, the retimer is configured to enter a low-delay mode.

17. The retimer according to claim 15 , wherein the first storage area is a storage area in a nonvolatile memory or firmware of the retimer.

18. The retimer according to claim 16 , wherein the retimer further comprising:
a link state machine, and each data processing circuit of the plurality of data processing circuits is configured to convert the training sequence processed by the link state machine into serial data.

19. The retimer according to claim 15 , wherein during the first link training, the control circuit is further configured to:
store the equalization parameter in a register; and, after the first link training is completed store, in the first storage area, the equalization parameter that is stored in the register.

20. The retimer according to claim 19 , wherein, during the second link training, the control

Assignees

• Huawei Tech Co Ltd

Inventors

• Li Yongyao
• Luo Fei
• Li Jiankang
• Wan Jie
• Jia Gongxian

Classifications

• G06F13/423 Primary

  with synchronous protocol · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• H04L25/03885

  adaptive · CPC title

• G06F13/4072 Primary

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title

• H04L25/03343

  Arrangements at the transmitter end · CPC title