Method, apparatus and system for encapsulating information in a communication

Patent metadata

Field	Value
Publication number	US-2016283433-A1
Application number	US-201514669295-A
Country	US
Kind code	A1
Filing date	Mar 26, 2015
Priority date	Mar 26, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

In one embodiment, a node includes at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in a first packet of a first communication protocol; a selection logic coupled to the first host device to receive the first packet and to provide the first packet to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic to receive the first packet under selection of the selection logic and to encapsulate the first packet into a second packet of a second communication protocol; and a second interface coupled to the conversion logic to receive the second packet and to communicate the second packet to a second device via a second interconnect of the second communication protocol. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . A system on chip (SoC) comprising:
at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in one or more first packets of a first communication protocol; a selection logic coupled to the first host device to receive the one or more first packets and to provide the one or more first packets to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic to receive the one or more first packets under selection of the selection logic and to encapsulate the one or more first packets into one or more second packets of a second communication protocol; and a second interface coupled to the conversion logic to receive the one or more second packets and to communicate the one or more second packets to a second device via a second interconnect of the second communication protocol.

2 . The SoC of claim 1 , wherein the first communication protocol comprises an enhanced serial peripheral interface protocol and the second communication protocol comprises a peripheral component interconnect express protocol.

3 . The SoC of claim 1 , wherein the second device comprises a second SoC or a central component to couple between the SoC and a shared resource, the shared resource to communicate according to the first communication protocol.

4 . The SoC of claim 3 , wherein the shared resource comprises a non-volatile storage to store a basic input/output system (BIOS), wherein the SoC is to receive boot code of the BIOS from the non-volatile storage via the second interconnect during initialization.

5 . The SoC of claim 3 , wherein the second interconnect is to operate at a default configuration prior to execution of the boot code.

6 . The SoC of claim 1 , wherein the first interface is to be disabled when the first interface is not coupled to an external device.

7 . The SoC of claim 1 , wherein the SoC is to be incorporated into a multi-node system including a plurality of SoCs, wherein a first SoC of the plurality of SoCs includes a first interface to communicate according to the first communication protocol, the first SoC to directly couple to a first shared resource via an interconnect of the first communication protocol, and others of the plurality of SoCs include a first interface to communicate according to the first communication protocol that is unconnected.

8 . The SoC of claim 1 , wherein the first host device is coupled to a first bus and is enumerated with a first device identifier.

9 . The SoC of claim 8 , wherein the second interface is coupled to the first bus and is enumerated with a second device identifier.

10 . The SoC of claim 1 , wherein the selection logic is to receive one or more third packets of the first communication protocol from the conversion logic and to send the one or more third packets to the first host device.

11 . The SoC of claim 10 , wherein the conversion logic is to receive one or more fourth packets of the second communication protocol from the second interface and to decapsulate the one or more third packets of the first communication protocol from the one or more fourth packets of the second communication protocol.

12 . The SoC of claim 1 , wherein the conversion logic is to include a tunnel indicator in a header of the one or more second packets of the second communication protocol to indicate presence of the encapsulated one or more first packets of the first communication protocol.

13 . A machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate an integrated circuit to perform a method comprising:
receiving a first packet in a selection logic of the integrated circuit from a host device of the integrated circuit, the host device to communicate in compliance with a first communication protocol, and selectively providing the first packet to a first interface of the integrated circuit when the integrated circuit is adapted within a system having a first device coupled to the first interface via a first interconnect compliant with the first communication protocol, otherwise selectively providing the first communication packet to a first logic of the integrated circuit; when the first packet is provided to the first logic, encapsulating, in the first logic, the first packet into a second packet compliant with a second communication protocol; and communicating the second packet to a second interface of the integrated circuit, the second interface to communicate the second packet to a second device compliant with the first communication protocol, via a second interconnect coupled to the integrated circuit, the second interconnect compliant with the second communication protocol.

14 . The machine readable medium of claim 13 , wherein the method further comprises disabling the first interface when the integrated circuit is implemented in a system not having the first device coupled to the first interface.

15 . The machine readable medium of claim 13 , wherein encapsulating the first packet into the second packet comprises:
setting a tunnel indicator of a header of the second packet; incorporating a cycle type of a header of the first packet into a cycle type field of the header of the second packet; and placing data of the first packet into a data portion of the second packet.

16 . The machine readable medium of claim 13 , wherein the method further comprises:
initializing the second interconnect to be in a default configuration after a reset; receiving boot code from the second device via the second interconnect; and re-initializing the second interconnect to a second configuration responsive to execution of the boot code.

17 . A system comprising:
a plurality of nodes each including a processor, the plurality of nodes to communicate with each other via a second communication protocol; and a device to be shared by at least some of the plurality of nodes, wherein the device is to communicate according to a first communication protocol, and a first node of the plurality of nodes is adapted to route first packets of the first communication protocol received from the device when the device is locally coupled to the first node to a second node of the plurality of nodes via second packets of the second communication protocol, and when the device is not locally coupled to the first node, the first node is to receive third packets of the second communication protocol and decapsulate from the third packets of the second communication protocol second packets of the first communication protocol directed to the first node from the device.

18 . The system of claim 17 , further comprising a fabric to couple the plurality of nodes via a first set of interconnects of the second communication protocol, wherein the first node and the second node are coupled to the fabric.

19 . The system of claim 17 , further comprising a central controller coupled to the first node and the second node, wherein the device is locally coupled to the central controller.

20 . The system of claim 19 , wherein the central controller is adapted to provide shared access to the device by the plurality of nodes, the central controller including a conversion logic to receive communications from the plurality of nodes according to the second communication protocol, convert the communications to decapsula

Assignees

• Intel Corp

Inventors

• Nair Mohan K
• Thomas Brent D
• Krithivas Ramamurthy

Classifications

• G06F9/4411

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F2213/0026

  PCI express · CPC title