System, Apparatus And Method For Link Training For A Multi-Drop Interconnect

Patent metadata

Field	Value
Publication number	US-2018293196-A1
Application number	US-201715483079-A
Country	US
Kind code	A1
Filing date	Apr 10, 2017
Priority date	Apr 10, 2017
Publication date	Oct 11, 2018
Grant date	—

Abstract

In one embodiment, a host controller includes a read controller to adjust internal clock timing based on a timer value associated with a first device and communicate information on an interconnect with the first device according to the adjusted clock timing. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . An apparatus comprising:
a host controller to couple to an interconnect to which a plurality of devices may be coupled, the host controller including:
a first driver to drive first information onto the interconnect;
a first receiver to receive second information from at least one of the plurality of devices via the interconnect;
a read controller to adjust timing of a read clock based on a propagation delay timer value associated with a first device of the plurality of devices and communicate information on the interconnect with the first device using the adjusted read clock timing; and
a link training controller to initiate a link training with the first device to determine the propagation delay timer value.

2 . The apparatus of claim 1 , wherein the host controller comprises a table having a plurality of entries each to store a propagation delay timer value for one of the plurality of devices.

3 . The apparatus of claim 1 , wherein the link training controller is to dynamically determine the propagation delay timer value for the first device.

4 . The apparatus of claim 1 , wherein the link training controller is to send a link training command to the first device to cause the first device to send an acknowledgement command to the host controller.

5 . The apparatus of claim 4 , wherein the link training controller is to determine the propagation delay timer value based on a time duration between a first time that the host controller is to send the link training command and a second time that the host controller is to receive the acknowledgement command.

6 . The apparatus of claim 5 , further comprising a timer to count the time duration according to a second clock, the second clock having a frequency substantially greater than the read clock.

7 . The apparatus of claim 1 , wherein the link training controller is to send a second propagation delay timer value associated with a second device of the plurality of devices, and the read controller is to adjust the timing of the read clock based on the second propagation delay timer value and communicate second information on the interconnect with the second device using the adjusted read clock timing, wherein the second propagation delay timer value is different than the propagation delay timer value.

8 . The apparatus of claim 1 , wherein the read controller comprises a first programmable circuit to adjust the read clock using the propagation delay timer value.

9 . The apparatus of claim 8 , wherein the host controller further comprises a write controller having a second programmable circuit to adjust a write clock to be provided to a write circuit of the host controller according to the propagation delay timer value, to maintain an inter-packet gap between a cycle of the write clock and a cycle of the read clock.

10 . The apparatus of claim 1 , wherein the link training controller is to dynamically determine a unique propagation delay timer value for the plurality of devices after the plurality of devices have been enumerated with address information.

11 . At least one computer readable storage medium comprising instructions that when executed enable a system to:
identify, via a host controller, a slave device having control of a bus that couples the slave device and the host controller; access a timer storage based on the identified slave device to obtain a timer value associated with the slave device; adjust a timing of a read clock based on the timer value; and read data received in the host controller from the slave device according to the adjusted timing of the read clock.

12 . The at least one computer readable storage medium of claim 11 , further comprising instructions that when executed enable the system to dynamically determine the timer value for the slave device based on a training.

13 . The at least one computer readable storage medium of claim 12 , wherein the training comprises to send a first command from the host controller to the slave device to cause the slave device to send an acknowledgement command to the host controller.

14 . The at least one computer readable storage medium of claim 13 , further comprising instructions that when executed enable the system to determine the timer value based on a time duration between a first time at which the host controller sends the first command and a second time at which the host controller receives the acknowledgment command.

15 . The at least one computer readable storage medium of claim 14 , further comprising instructions that when executed enable the system to measure the time duration according to a clock signal having a higher clock rate than the read clock.

16 . The at least one computer readable storage medium of claim 11 , further comprising instructions that when executed enable the system to communicate with a second slave device coupled to the host controller via the bus according to a second timer value, the second timer value different than the timer value, wherein the second slave device is located at a second distance with respect to the host controller, the first device located at a first distance with respect to the host controller, the first distance less than the second distance, the timer value less than the second timer value.

17 . A system comprising:
a first device coupled to a host controller via a bus, wherein the first device is a first distance from the host controller; a second device coupled to the host controller via the bus, wherein the second device is a second distance from the host controller, the second distance greater than the first distance; and the host controller having a read controller to read data communicated from the first device with a read clock, a timing of the read clock adjusted according to a timer value associated with the first device.

18 . The system of claim 17 , wherein the host controller comprises a table and a link training controller, the link timing controller to obtain the timer value from the table.

19 . The system of claim 18 , wherein the link training controller is to send a first command to the first device to cause the first device to send an acknowledgement command to the host controller, and determine the timer value based on a time duration between a first time that the host controller is to send the first command and a second time that the host controller is to receive the acknowledgement command.

20 . The system of claim 19 , further comprising a timer to measure the time duration according to a second clock, the second clock having a higher clock rate than the read clock.

Assignees

• Intel Corp

Inventors

• Srivastava Amit Kumar
• Quiet Duane G
• Foust Kenneth P

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/364 Primary

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• G06F13/404

  with address mapping · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• G06F13/4072

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title