Synchronized parallel tile computation for large area lithography simulation

US11747786B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11747786-B2
Application numberUS-202217750828-A
CountryUS
Kind codeB2
Filing dateMay 23, 2022
Priority dateNov 15, 2017
Publication dateSep 5, 2023
Grant dateSep 5, 2023

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Abstract

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Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

First claim

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What is claimed is: 1. A system comprising: a manager machine interacting with a plurality of worker machines, wherein the manager machine is configured to: receive an IC design layout; partition the IC design layout into a plurality of tiles; assign the plurality of tiles to the plurality of worker machines; and wherein the plurality of worker machines interact with the manager machine and are configured to synchronize image values from the plurality of tiles; wherein the manager machine is further configured to: generate a modified IC design layout by combining final synchronized image values from the plurality of worker machines; and provide the modified IC design layout for fabricating a mask. 2. The system of claim 1 , wherein the plurality of worker machines are configured to execute a plurality of imaging steps, each of the plurality of the imaging steps includes the synchronizing of the image values from the plurality of tiles. 3. The system of claim 2 , wherein a first worker machine of the plurality of worker machines is configured to: in a first imaging step of the plurality of imaging steps, compute image value A of a pixel in an overlapped region of the plurality of tiles, and exchanging the image value A with a second worker machine of the plurality of worker machines, and in a second imaging step of the plurality of imaging steps, compute image value C of the pixel; and wherein the second worker machine is configured to: in the first imaging step, compute image value B of the pixel, and exchanging the image value B with the first worker machine, and in the second imaging step, compute image value D of the pixel, and wherein the computing of the image value C and the computing of the image value D are both based on a weighted combination of the image value A and the image value B. 4. The system of claim 3 , wherein the weighted combination of the image value A and the image value B uses a first weight multiplied by the image value A and a second weight multiplied by the image value B, and wherein a sum of the first and second weights equals one, wherein the image value C and the image value D are equal, and wherein the first and second worker machines are further configured to send the image value C and the image value D to the manager machine. 5. The system of claim 4 , wherein the first weight equals the second weight at a middle-point of the overlapped region. 6. The system of claim 1 , wherein the manager machine is a first manager machine, and the system further includes a second manager machine interacting with another plurality worker machines. 7. The system of claim 1 , wherein each tile in the plurality of tiles has a core region, an overlapped region, and a halo region, the core and overlapped regions having a weight function that equals one and the halo region having a weight function that equals zero. 8. The system of claim 7 , wherein the weight function of the overlapped region is based on a weighted combination of image values taken at the overlapped region from neighboring tiles in the plurality of tiles. 9. A system, comprising: a first worker machine configured to receive a first tile of an IC layout and compute a first image value of a point in the first tile; a second worker machine configured to receive a second tile of the IC layout and compute a second image value of the point in the second tile, wherein the point is in an overlapped region between the first and second tiles; and a communication module configured to exchange the computed first and second image values between the first and second worker machines, wherein the first worker machine is further configured to compute an updated first image value based on a weighted combination of the first and second image values. 10. The system of claim 9 , wherein the second worker machine is further configured to compute an updated second image value based on a weighted combination of the first and second image values. 11. The system of claim 10 , wherein the updated first image value equals the updated second image value. 12. The system of claim 10 , wherein the first and second worker machines compute the first and second updated image values in parallel. 13. The system of claim 10 , wherein the weighted combination of the first and second image value uses a first weight multiplied by the first image value and a second weight multiplied by the second image value, wherein a sum of the first and second weights equal 1. 14. The system of claim 13 , wherein the first weight equals the second weight at a middle-point of the overlapped region. 15. The system of claim 13 , further comprising: a third worker machine configured to receive a third tile of an IC layout and compute a third image value of the point in the first tile, the third worker machine further configured to receive the updated first image value from the first worker machine through the communication module, wherein the third worker machine is further configured to compute an updated third image value based on a weighted combination of the third image value and the updated first image value. 16. A system comprising: a manager machine interacting with a plurality of worker machines, wherein the manager machine is configured to: receive an IC design layout; partition the IC design layout into a first and a second tile; assign the first tile to a first worker machine and the second tile to a second worker machine; define an overlapping region between the first and the second tile, the overlapping region having a plurality of pixels; send delivery instructions to the first and second worker machine regarding the plurality of pixels, thereby enabling the first and second worker machine to exchange information with each other for synchronizing image values of the plurality of pixels; generate a first modified IC design layout by combining image values of the first and second tile having the synchronized image values from the first and second worker machines; and provide the first modified IC design layout for fabricating a mask. 17. The system of claim 16 , wherein the first modified IC design layout is stored in the first and second worker machines. 18. The system of claim 16 , wherein the manager machine is further configured to pre-process the IC design layout through rasterization or anti-aliasing filtering. 19. The system of claim 16 , wherein the system further comprises a second manager machine interacting with a second plurality of worker machines, wherein the second manager machine is configured to generate a second modified IC design layout by combining synchronized image values from a third and fourth worker machine, wherein the second modified IC design layout is combined with the first modified IC design layout for fabricating the mask. 20. The system of claim 19 , wherein the second modified IC design layout is stored in the third and fourth worker machines.

Assignees

Inventors

Classifications

  • characterised by using design data to control NC machines, e.g. CAD/CAM (G05B19/4093 takes precedence) · CPC title

  • Reflection masks; Preparation thereof · CPC title

  • G03F1/36Primary

    Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

  • Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

  • Floor-planning or layout, e.g. partitioning or placement · CPC title

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What does patent US11747786B2 cover?
Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a m…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification G05B19/4097. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 05 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).