System and method for thermally calibrating semiconductor process chambers

US11747209B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11747209-B2
Application numberUS-202016923717-A
CountryUS
Kind codeB2
Filing dateJul 8, 2020
Priority dateSep 10, 2018
Publication dateSep 5, 2023
Grant dateSep 5, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A system and method for thermally calibrating semiconductor process chambers is disclosed. In various embodiments, a first non-contact temperature sensor can be calibrated to obtain a first reading with the semiconductor process chamber. The first reading can be representative of a first temperature at a first location. The first non-contact temperature sensor can be used to obtain a second reading representative of a second temperature of an external thermal radiation source. The second temperature of the external thermal radiation source can be adjusted to a first temperature setting of the external radiation source such that the second reading substantially matches the first reading. Additional non-contact temperature sensor(s) can be directed at the external thermal radiation source and can be adjusted such that the reading(s) of the additional non-contact sensors are calibrated and matched to one another.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor processing system comprising: a first semiconductor process chamber; a first non-contact temperature sensor configured to measure a first temperature of a portion of the first semiconductor process chamber or of a first wafer within the first semiconductor process chamber; a second semiconductor process chamber that is of the same type as the first semiconductor process chamber; and a second non-contact temperature sensor configured to measure a second temperature of a portion of the second semiconductor process chamber or of a second wafer within the second semiconductor process chamber, wherein the first non-contact temperature sensor calibrates an external thermal radiation source. 2. The system of claim 1 , wherein the first and second semiconductor process chambers comprise chemical vapor deposition (CVD) reactors. 3. The system of claim 1 , further comprising the external thermal radiation source. 4. The system of claim 3 , wherein the external thermal radiation source comprises a blackbody furnace. 5. The system of claim 1 , wherein the first and second non-contact temperature sensors comprise optical pyrometers. 6. The system of claim 1 , wherein the first and second semiconductor process chambers comprise atomic layer deposition (ALD) reactors. 7. The system of claim 1 , wherein each of the first and second semiconductor process chambers comprises a substrate support configured to support the respective first wafer or second wafer. 8. The system of claim 1 , wherein each of the first and second semiconductor process chambers comprises a heating system. 9. The system of claim 8 , wherein each of the first and second semiconductor process chambers comprises a temperature controller configured to control a temperature within the respective semiconductor process chamber based on one or more respective feedback signals received from the first and second non-contact temperature sensors and/or based on one or more respective signals received from the heating system. 10. The system of claim 9 , wherein the temperature controller comprises processing electronics configured to process temperature data, and based on the processed temperature data, to send an actuation signal to the heating system to increase or decrease the temperature of the respective semiconductor process chamber. 11. The system of claim 8 , wherein the heating system comprises a plurality of linear radiant heating elements. 12. The system of claim 1 , wherein each of the first and second semiconductor process chambers comprises a quartz wall. 13. The system of claim 1 , wherein the external thermal radiation source is a single external thermal radiation source. 14. A semiconductor processing system comprising: a first semiconductor process chamber; a first non-contact temperature sensor configured to measure a first temperature of a portion of the first semiconductor process chamber or of a first wafer within the first semiconductor process chamber; an external thermal radiation source, wherein the external thermal radiation source is calibrated relative to a measurement from the first non-contact temperature sensor; a second semiconductor process chamber; and a second non-contact temperature sensor configured to measure a second temperature of a portion of the second semiconductor process chamber or of a second wafer within the second semiconductor process chamber, wherein the second non-contact temperature sensor is calibrated relative to the external thermal radiation source. 15. The system of claim 14 , wherein one or more of the first and second semiconductor process chambers comprise chemical vapor deposition (CVD) reactors. 16. The system of claim 14 , wherein one or more of the first and second semiconductor process chambers comprise atomic layer deposition (ALD) reactors. 17. The system of claim 14 , wherein each of the first and second semiconductor process chambers comprise a substrate support configured to support the respective first wafer or second wafer. 18. The system of claim 14 , wherein each of the first and second semiconductor process chambers comprises a heating system. 19. The system of claim 18 , wherein each of the first and second semiconductor process chambers comprises a temperature controller configured to control a temperature within the respective semiconductor process chamber based on one or more respective feedback signals received from the first and second non-contact temperature sensors and/or based on one or more respective signals received from the heating system. 20. A semiconductor processing system comprising: a first semiconductor process chamber; a first non-contact temperature sensor configured to measure a first temperature of a portion of the first semiconductor process chamber or of a first wafer within the first semiconductor process chamber; an external radiation source, wherein the external radiation source is configured to mimic one or more characteristics of the first semiconductor process chamber; a second non-contact temperature sensor configured to measure a second temperature portion of the first semiconductor process chamber or of the first wafer within the first semiconductor process chamber, wherein the second non-contact temperature sensor is calibrated relative to the external radiation source; a second semiconductor process chamber; and a third non-contact temperature sensor configured to measure a third temperature of a portion of the second semiconductor process chamber or of a second wafer within the second semiconductor process chamber, wherein the third non-contact temperature sensor is calibrated relative to the external radiation source.

Assignees

Inventors

Classifications

  • characterised by multiple measurements, corrections, marking or sorting processes · CPC title

  • Temperature monitoring · CPC title

  • mainly by radiation · CPC title

  • Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

  • G01J5/00Primary

    Radiation pyrometry, e.g. infrared or optical thermometry · CPC title

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What does patent US11747209B2 cover?
A system and method for thermally calibrating semiconductor process chambers is disclosed. In various embodiments, a first non-contact temperature sensor can be calibrated to obtain a first reading with the semiconductor process chamber. The first reading can be representative of a first temperature at a first location. The first non-contact temperature sensor can be used to obtain a second rea…
Who is the assignee on this patent?
Asm Ip Holding Bv, Asm Ip Holding Bv
What technology area does this patent fall under?
Primary CPC classification H10P72/0602. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 05 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).