Display device

Patent metadata

Field	Value
Publication number	US-11744111-B2
Application number	US-202217839864-A
Country	US
Kind code	B2
Filing date	Jun 14, 2022
Priority date	Mar 23, 2016
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

A plurality of thin film transistors provided in a peripheral region are first staggered thin film transistors where a first channel layer configured of low-temperature polysilicon is included, and the first channel layer is not interposed between a first source electrode and a first gate electrode, and between a first drain electrode and the first gate electrode. A plurality of thin film transistors provided in a display region are second staggered thin film transistors where a second channel layer configured of an oxide semiconductor is included, and the second channel layer is not interposed between a second source electrode and a second gate electrode, and between a second drain electrode and the second gate electrode. The first thin film transistor is located below the second thin film transistor.

First claim

What is claimed is:

1. A display device comprising:
a pixel electrode that is provided in a display region configured to display an image;
a common electrode that is disposed above the pixel electrode;
a light-emitting element layer that is interposed between the pixel electrode and the common electrode;
a first thin film transistor including a first gate electrode coupled to the pixel electrode in the display region, no other transistor being coupled between the first thin film transistor and the pixel electrode;
a first conductive layer that is provided under and overlaps with the first thin film transistor;
a circuit layer that is provided in a peripheral region outside the display region; and
a second thin film transistor including a second gate electrode in the circuit layer,
wherein a first channel of the first thin film transistor is made of an oxide semiconductor, and the second thin film transistor is positioned at a lower layer in comparison with the first thin film transistor, and the second gate electrode is in the same layer as the first conductive layer.

2. The display device according to claim 1 , wherein a second channel layer of the second thin film transistor is made of a portion of a low-temperature poly silicon layer.

3. The display device according to claim 2 , further comprising a second conductive layer that is composed of another portion of the low-temperature polysilicon layer with ions injected therein in the display region, wherein the first conductive layer overlaps the second conductive layer.

4. The display device according to claim 3 , wherein the second conductive layer is in the same layer as the second channel layer.

5. The display device according to claim 2 , further comprising a second conductive layer that is formed by injecting ions into the low-temperature polysilicon layer in the display region, wherein the first conductive layer overlaps the second conductive layer.

Assignees

• Japan Display Inc

Inventors

• Maruyama Satoshi

Classifications

• H10D30/0312

  characterised by the gate electrodes · CPC title

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title