Array substrate, its manufacturing method and display device

Patent metadata

Field	Value
Publication number	US-9627461-B2
Application number	US-201514771320-A
Country	US
Kind code	B2
Filing date	Jan 16, 2015
Priority date	Sep 25, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

The present disclosure provides an array substrate, its manufacturing method and a display device. The array substrate includes a thin film transistor. A source electrode and a drain electrode are located above a pattern of an active layer, and the source electrode and the drain electrode are in electrical contact with the pattern of the active layer through a first via-hole penetrating an insulating structure. Before the formation of the source electrode and the drain electrode, the pattern of the active layer is subjected to ion injection through the first via-hole, so as to form an ion injection region.

First claim

What is claimed is:

1. A method for manufacturing an array substrate, comprising a step of forming a thin film transistor (TFT); wherein the step of forming the TFT comprises:
forming a pattern of an active layer on a substrate;
forming an insulating structure on the pattern of the active layer;
forming a first via-hole penetrating the insulating structure so as to expose the pattern of the active layer at a position corresponding to the first via-hole, the first via-hole extending to an interior of the exposed pattern of the active layer;
subjecting the exposed pattern of the active layer to ion injection through the first via-hole, so as to form an ion injection region located in pattern of the active layer; and
forming a source electrode and a drain electrode on the insulating structure, the source electrode and the drain electrode being in contact with a surface of the ion injection region through the first via-hole so as to be electrically connected to the pattern of the active layer.

2. The method according to claim 1 , wherein the insulating structure comprises at least two insulating layers.

3. The method according to claim 1 , wherein the step of forming the insulating structure on the pattern of the active layer comprises forming a gate insulating layer and an interlayered insulating layer.

4. The method according to claim 3 , further comprising forming a gate electrode between the gate insulating layer and the interlayered insulating layer; wherein the gate electrode is arranged on the gate insulating layer at a position corresponding to the pattern of the active layer.

5. The method according to claim 3 , further comprising forming a storage capacitor; wherein the gate insulating layer is an insulating medium for the storage capacitor.

6. The method according to claim 5 , further comprising:
step 1 of forming a poly-Si film on the substrate, and forming the pattern of the active layer and a pattern of a first electrode of the storage capacitor by a patterning process;
step 2 of applying photoresist onto the pattern of the active layer and the pattern of the first electrode of the storage capacitor, and exposing and developing the photoresist so as to expose a region of the pattern of the active layer other than a channel region of the active layer, and the pattern of the first electrode of the storage capacitor;
step 3 of subjecting the region of the pattern of the active layer other than the channel region of the active layer and the pattern of the first electrode of the storage capacitor to ion injection using the photoresist as a mask plate, so as to form a first doped poly-Si active layer and a second doped poly-Si active layer, the second doped poly-Si active layer serving as the first electrode of the storage capacitor;
step 4 of forming the gate insulating layer on the pattern of the active layer and the pattern of the first electrode of the storage capacitor;
step 5 of forming a gate metal layer on the gate insulating layer, and forming the gate electrode and a pattern of a second electrode of the storage capacitor by a patterning process;
step 6 of forming the interlayered insulating layer on the gate electrode and the pattern of the second electrode of the storage capacitor;
step 7 of forming the first via-hole penetrating the gate insulating layer and the interlayered insulating layer, so as to expose the first doped poly-Si active layer at a position corresponding to the first via-hole, the first via-hole extending to an interior of the exposed first doped poly-Si active layer;
step 8 of subjecting the exposed first doped poly-Si active layer to ion injection through the first via-hole, so as to form an ion injection region; and
step 9 of forming the source electrode and the drain electrode on the interlayered insulating layer, the source electrode and the drain electrode being in contact with a surface of the ion injection region through the first via-hole, and thereby in electrical contact with the first doped poly-Si active layer.

7. The method according to claim 5 , wherein the array substrate is an active matrix organic light-emitting diode (AMOLED) array substrate, and the method further comprises:
forming a planarization layer on the source electrode and the drain electrode;
forming a second via-hole in the planarization layer, so as to expose the drain electrode; and
forming a cathode of an organic light-emitting diode on the planarization layer, the cathode being in electrical contact with the drain electrode through the second via-hole, and the storage capacitor being electrically connected to the cathode.

8. The method according to claim 1 , wherein the first via-hole extends to a depth located within the interior of the exposed pattern of the active layer.

9. An array substrate comprising a thin film transistor (TFT); wherein the TFT comprises:
a pattern of an active layer on a substrate;
an insulating structure covering the pattern of the active layer, a first via-hole being formed in the insulating structure and extending to an interior of an exposed pattern of the active layer;
an ion injection region located in the pattern of the active layer and at a position corresponding to the first via-hole; and
a source electrode and a drain electrode arranged on the insulating structure, the source electrode and the drain electrode being in contact with a surface of the ion injection region through the first via-hole so as to be electrically connected to the pattern of the active layer.

10. The array substrate according to claim 9 , wherein the insulating structure comprises at least two insulating layers.

11. The array substrate according to claim 9 , wherein the insulating structure comprises a gate insulating layer and an interlayered insulating layer.

12. The array substrate according to claim 11 , wherein a gate electrode is arranged between the gate insulating layer and the interlayered insulating layer, and on the gate insulating layer at a position corresponding to the pattern of the active layer.

13. The array substrate according to claim 12 , further comprising a storage capacitor; wherein the gate insulating layer serves as an insulating medium for the storage capacitor.

14. The array substrate according to claim 13 , further comprising a pattern including the active layer and a first electrode of the storage capacitor arranged on the substrate;
wherein the pattern of the active layer comprising a poly-Si active layer, first doped poly-Si active layers located at two sides of the poly-Si active layer and the ion injection region; wherein the ion injection region is arranged in the first doped poly-Si active layers, the pattern of the first electrode of the storage capacitor is subjected to ion injection so as to form a second doped poly-Si active layer as the first electrode of the storage capacitor;
wherein the gate insulating layer covers the pattern of the active layer and the pattern of the first electrode of the storage capacitor;
wherein the gate electrode and a second electrode of the storage capacitor are arranged on the gate insulating layer, and formed by an identical gate metal layer;
wherein the interlayered insulating layer covers the gate electrode and the second electrode of the storage capacitor; the first via-hole penetrates the gate insulating layer and the interlayered layer and extends to an interior of the ion injection region; and
wherein the source electrode and the drain electrode are arranged on the interlayered insulating layer, the source electrode and the drain electrode are in contact with the surface of the ion injection region through the firs

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Xie Zhenyu

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H01L27/1288

  Electricity · mapped topic

• H01L27/3258

  Electricity · mapped topic

• H01L27/3276

  Electricity · mapped topic

• H01L21/77

  Electricity · mapped topic