Fabrication of a majority logic gate having non-linear input capacitors

Patent metadata

Field	Value
Publication number	US-11742860-B2
Application number	US-202217808290-A
Country	US
Kind code	B2
Filing date	Jun 22, 2022
Priority date	May 21, 2021
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.

First claim

We claim:

1. An apparatus comprising:
a first metal line of a first metal layer;
a second metal layer, wherein the second metal layer is higher than the first metal layer;
a first capacitor on the first metal line, wherein the first capacitor is further coupled to a first input line of the second metal layer;
a second capacitor on the first metal line, wherein the second capacitor is further coupled to a second input line of the second metal layer;
a third capacitor on the first metal line, wherein the third capacitor is further coupled to a third input line of the second metal layer, wherein the first capacitor, the second capacitor, and the third capacitor comprise non-linear polar material;
a via coupled to the first metal line, the via being under the first metal line; and
an active device having a gate electrode, wherein the gate electrode is coupled to the via.

2. The apparatus of claim 1 , wherein the active device includes a source region and a drain region, wherein the source region is coupled to supply line.

3. The apparatus of claim 1 , wherein the first capacitor, the second capacitor, and the third capacitor are coupled such that there is substantial rail-to-rail voltage on the first metal line to reduce static leakage in the active device.

4. The apparatus of claim 1 , wherein the first metal line extends orthogonal to the first input line.

5. The apparatus of claim 1 , wherein the first capacitor, the second capacitor, and the third capacitor are positioned between the first metal layer and the second metal layer.

6. The apparatus of claim 1 , wherein the non-linear polar material includes one of: ferroelectric material, paraelectric material, or non-linear dielectric.

7. The apparatus of claim 6 , wherein the ferroelectric material includes one of:
bismuth ferrite (BFO) with a first doping material, wherein the first doping material is one of Lanthanum or elements from lanthanide series of periodic table;
lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a relaxor ferroelectric which includes one of lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), Barium Titanium-Bismuth Zinc Niobium Tantalum (BT-BZNT), or Barium Titanium-Barium Strontium Titanium (BT-BST);
a perovskite which includes one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3;
a hexagonal ferroelectric which includes one of: YMnO3 or LuFeO3;
hexagonal ferroelectrics of a type h-RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);
hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides;
hafnium oxides as Hf1-x Ex Oy, where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y;
Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N or Al(1-x-y)Mg(x)Nb(y)N, y doped HfO2, where x includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein ‘x’ or ‘y’ is a fraction;
niobate type compounds LiNbO3, LiTaO3, Lithium iron Tantalum Oxy Fluoride, Barium Strontium Niobate, Sodium Barium Niobate, or Potassium strontium niobate; or
an improper ferroelectric which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 to 100.

8. The apparatus of claim 6 , wherein the paraelectric material includes one of: SrTiO3, Ba(x)Sr(y)TiO3, HfZrO2, Hf-Si-O, La-substituted PbTiO3, or PMN-PT based relaxor ferroelectrics.

9. The apparatus of claim 6 , wherein the paraelectric material includes one of: Sr, Ti, Ba, Hf, Zr, Si, La, or Pb.

10. The apparatus of claim 1 , wherein signals on the first input line, the second input line, and the third input line are digital signals, and wherein the first metal line has a voltage which is either at ground level or a supply level.

11. The apparatus of claim 1 , wherein when the third input line is at ground level, a voltage on the first metal line is an AND logic function of signals on the first input line and the second input line.

12. The apparatus of claim 1 , wherein when the third input line is at supply level, a voltage on the first metal line is an OR logic function of signals on the first input line and the second input line.

13. A method comprising:
forming a first metal line of a first metal layer;
forming a second metal layer, wherein the second metal layer is higher than the first metal layer;
forming a first capacitor on the first metal line, wherein the first capacitor is further coupled to a first input line of the second metal layer;
forming a second capacitor on the first metal line, wherein the second capacitor is further coupled to a second input line of the second metal layer;
forming a third capacitor on the first metal line, wherein the third capacitor is further coupled to a third input line of the second metal layer, wherein the first capacitor, the second capacitor, and the third capacitor comprise non-linear polar material;
forming a via coupled to the first metal line, the via being under the first metal line; and
forming an active device having a gate electrode, wherein the gate electrode is coupled to the via.

14. The method of claim 13 , wherein the active device includes a source region and a drain region, wherein the source region is coupled to supply line.

15. The method of claim 13 , wherein the first capacitor, the second capacitor, and the third capacitor are coupled such that there is substantial rail-to-rail voltage on the first metal line to reduce static leakage in the active device.

16. The method of claim 13 , wherein the first metal line extends orthogonal to the first input line, and wherein the first capacitor, the second capacitor, and the third capacitor are positioned between the first metal layer and the second metal layer.

17. A system comprising:
a memory circuitry to store one or more instructions;
a processor circuitry coupled to the memory circuitry; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the processor circuitry comprises:
a first metal line of a first metal layer;
a second metal layer, wherein the second metal layer is higher than the first metal layer;
a first capacitor on the first metal line, wherein the first capacitor is further coupled to a first input line of the second metal layer;
a second capacitor on the first metal line, wherein the second capacitor is further coupled to a second input line of the second metal layer;
a third capacitor on the first metal line, wherein the third capacitor is further coupled to a third input line of the second metal layer, wherein the first capacitor, the second capacitor, and the third capacitor comprise non-linear polar material;
a via coupled to the first metal line, the via being under the first metal line; and
an active device having a gate electrode, wherein the gate electrode is coupled to the via.

Assignees

• Kepler Computing Inc

Inventors

• Manipatruni Sasikanth
• Rios Rafael
• Reynolds Neal
• Odinaka Ikenna
• Menezes Robert
• Dokania Rajeev Kumar
• Ramesh Ramamoorthy
• Mathuriya Amrita

Classifications

• H10D1/694

  comprising noble metals or noble metal oxides · CPC title

• H10D1/682 Primary

  having dielectrics comprising perovskite structures · CPC title

• H03K19/23 Primary

  Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs · CPC title

• H01L28/55

  Electricity · mapped topic

• H03K19/0013

  in field effect transistor circuits · CPC title