Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory

Patent metadata

Field	Value
Publication number	US-10998077-B2
Application number	US-201916702744-A
Country	US
Kind code	B2
Filing date	Dec 4, 2019
Priority date	Jan 8, 2019
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

First claim

What is claimed is:

1. A circuit, comprising:
a decoder coupled to a memory address bus and configured to receive and decode a memory address to selectively drive a plurality of select lines of a memory;
an encoding circuit configured to encode data on said plurality of select lines to generate an encoded address on an encoded address bus;
a comparison circuit coupled to the encoded address bus and the memory address bus and configured to compare the encoded address to the memory address and generate a test result signal in response to the comparison which is indicative of whether the decoder is operating properly;
a blocking circuit configured to block passage of the encoded address to a portion of the encoded address bus coupled to the comparison circuit in response to a test control signal; and
a testing control circuit configured to generate the test control signal and apply a force signal to said portion of the encoded address bus, with said memory address bus configured to receive a test signal provided by a memory built-in self-test (MBIST) scan routine, the force signal and the test signal being configured to the test the comparison circuit so that the test result signal generated by the comparison circuit in response to the comparison is indicative of whether the comparison circuit itself is operating properly.

2. The circuit of claim 1 , wherein the testing control circuit is selectively enabled to generate the test control signal and the force signal in response to a subset of the memory built-in self-test (MBIST) scan routine.

3. The circuit of claim 1 , wherein the comparison circuit comprises a plurality of bit comparator circuits configured to compare bits of the memory address bus to corresponding bits of the encoded address bus, and wherein the test signal from the MBIST scan routine selectively picks one bit comparator circuit of the plurality of bit comparator circuits to be tested for operating properly.

4. The circuit of claim 1 , wherein the comparison circuit comprises a plurality of bit comparator circuits configured to compare bits of the memory address bus to corresponding bits of the encoded address bus, and wherein the MBIST scan routine provides a sequence of test signals, each test signal in the sequence configured to pick a different bit comparator circuit of the plurality of bit comparator circuits to be tested for operating properly.

5. The circuit of claim 1 , wherein the select lines comprise one or more of word lines for the memory or column multiplexer lines for the memory.

6. The circuit of claim 1 , wherein a logic state of the test result signal generated by the comparison circuit indicating that the decoder is operating properly and a logic state of the test result signal generated by the comparison circuit indicating that the comparison circuit itself is operating properly are different logic states.

7. The circuit of claim 1 , wherein a logic state of the test result signal generated by the comparison circuit indicating that the decoder is operating properly and a logic state of the test result signal generated by the comparison circuit indicating that the comparison circuit itself is operating properly are same logic states.

8. The circuit of claim 1 , wherein the blocking circuit is a tri-state blocking circuit configured to disconnect the portion of the encoded address bus in response to the test control signal.

9. The circuit of claim 1 , wherein the encoded address bus comprises a true bus portion and a complement bus portion, the true bus portion carrying the encoded address and the complement bus portion carrying a complement of the encoded address.

10. The circuit of claim 9 , wherein the force signal forces all bits of the true bus portion to a first logic state and all bits of the complement bus portion to a second logic state different from the first logic state.

11. The circuit of claim 1 , wherein the force signal forces all bits of the encoded address bus to a same logic state.

12. A method for testing a safety logic circuit of a memory, wherein the safety logic circuit includes a comparison circuit which operates to compare bits of an encoded address obtained by encoding data on a plurality of select lines of the memory to bits of a memory address for selecting a portion of the memory, said data generated in response to a decoding of the memory address, comprising:
performing a memory built-in self-test (MBIST) scan routine to test the memory; and
in response to a subset of the MBIST scan routine, testing the comparison circuit of the safety logic circuit by:
applying a force signal to the comparison circuit in substitution for the encoded address;
applying a test signal to the comparison circuit, wherein the test signal is provided by the MBIST scan routine;
comparing by the comparison circuit of the force signal to the test signal, wherein the force signal and the test signal are configured to test for proper operation of a bit comparator within the comparison circuit; and
generating a test result signal in response to the comparing by the comparison circuit that is indicative of whether said bit comparator of the comparison circuit is operating properly.

13. The method of claim 12 , wherein applying the force signal comprises blocking passage of the encoded address over an encoded address bus to the comparison circuit.

14. The method of claim 12 , further comprising evaluating the test result signal by the MBIST.

15. The method of claim 12 , wherein the comparison circuit comprises a plurality of bit comparators, and wherein the test signal selectively picks one bit comparator of the plurality of bit comparators to be tested for operating properly.

16. The method of claim 12 , wherein the comparison circuit comprises a plurality of bit comparators, and wherein applying the test signal comprises generating a sequence of test signals, each test signal in the sequence configured to pick a different bit comparator of the plurality of bit comparators to be tested for operating properly.

17. A circuit, comprising:
a memory circuit, comprising:
a decoder coupled to a memory address bus and configured to receive and decode a memory address to selectively drive a plurality of select lines of the memory circuit;
an encoding circuit configured to encode data on said plurality of select lines to generate an encoded address on an encoded address bus; and
a comparison circuit coupled to the encoded address bus and the memory address bus and configured to compare the encoded address to the memory address and generate a test result signal in response to the comparison which is indicative of whether the decoder is operating properly;

a memory built-in self-test (MBIST) circuit configured to test the memory circuit using an MBIST scan routine and to receive the test result signal; and
a testing circuit, comprising:
a control circuit operating responsive to a subset of the MBIST scan routine to generate a test control signal and a force signal; and
a blocking circuit configured to block passage of the encoded address to a portion of the encoded address bus coupled to the comparison circuit in response to the test control signal;
wherein the force signal is applied to said portion of the encoded address bus and a test signal from the subset of the MBIST scan routine is applied to the memory address bus, the force signal and the test signal being configured to the test the comparison circuit, the comparison circuit operating to compare the force signal to the test signal and generate the test result signal indicative of whethe

Assignees

• St Microelectronics Int Nv

Inventors

• Bhasin Rohit
• Kumar Shishir
• Roy Tanmoy
• Bihani Deepak Kumar

Classifications

• G11C29/32

  Serial access; Scan testing · CPC title

• G11C29/14

  Implementation of control logic, e.g. test mode decoders · CPC title

• G11C29/38 Primary

  Response verification devices · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/18 Primary

  Address generation devices; Devices for accessing memories, e.g. details of addressing circuits · CPC title