Non-volatile memory devices and systems with volatile memory features and methods for operating the same

Patent metadata

Field	Value
Publication number	US-11742028-B2
Application number	US-202218053201-A
Country	US
Kind code	B2
Filing date	Nov 7, 2022
Priority date	Apr 23, 2018
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

First claim

What is claimed is:

1. A memory device, comprising:
a non-volatile memory array;
a second memory separate from the non-volatile memory array; and
circuitry configured to:
store one or more addresses of the non-volatile memory array in the second memory;
detect a changed power condition of the memory device; and
degrade data at the one or more addresses of the non-volatile memory array in response to detecting the changed power condition by overwriting the data at the one or more addresses with a pseudorandom pattern.

2. The memory device of claim 1 , wherein the changed power condition is a power-on event, a power-off event, or a power-loss event.

3. The memory device of claim 1 , wherein the second memory comprises a write-once read-many (WORM) memory.

4. The memory device of claim 1 , wherein the circuitry is further configured to:
write the one or more addresses to the second memory in response to a command received at the memory device.

5. The memory device of claim 1 , wherein the second memory comprises an array of fuses, anti-fuses, or a combination thereof.

6. The memory device of claim 1 , wherein the second memory comprises an address register of the memory device.

7. The memory device of claim 1 , further comprising an energy storage mechanism.

8. The memory device of claim 7 , wherein the energy storage mechanism comprises a capacitor, a battery, a fuel cell, or a combination thereof.

9. The memory device of claim 7 , wherein the energy storage mechanism has an energy storage capacity sufficient to provide power for the duration of the degrading data at the one or more addresses.

10. The memory device of claim 1 , wherein the non-volatile memory array comprises NAND flash, NOR flash, MRAM, FeRAM, PCM, or a combination thereof.

11. The memory device of claim 1 , wherein a single semiconductor die comprises the non-volatile memory array, the second memory, and the circuitry.

12. The memory device of claim 1 , wherein a memory controller die comprises the circuitry and a memory die comprises the non-volatile memory array.

13. A method of operating a memory device including a non-volatile memory array and a second memory separate from the non-volatile memory array, the method comprising:
storing, in the second memory, one or more addresses of the non-volatile memory array;
detecting a changed power condition of the memory device; and
in response to the detection, degrading data at the one or more addresses of the non-volatile memory by overwriting the data at the one or more addresses with a pseudorandom pattern.

14. The method of claim 13 , wherein the changed power condition is a power-on event, a power-off event, or a power-loss event.

15. The method of claim 13 , wherein the second memory comprises a write-once read-many (WORM) memory.

16. The method of claim 13 , further comprising:
writing the one or more addresses to the second memory in response to a command received at the memory device.

17. The method of claim 13 , wherein the second memory comprises an array of fuses, anti-fuses, or a combination thereof.

18. The method of claim 13 , wherein the second memory comprises an address register of the memory device.

19. The method of claim 13 , wherein the non-volatile memory array comprises NAND flash, NOR flash, MRAM, FeRAM, PCM, or a combination thereof.

Assignees

• Micron Technology Inc

Inventors

• Cowles Timothy B
• Raad George B
• Rehmeyer James S
• Parry Jonathan S

Classifications

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C11/165

  Auxiliary circuits · CPC title

• G11C11/1653

  Address circuits or decoders · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/1697

  Power supply circuits · CPC title