Non-volatile memory devices and systems with volatile memory features and methods for operating the same

Patent metadata

Field	Value
Publication number	US-11495299-B2
Application number	US-202117339846-A
Country	US
Kind code	B2
Filing date	Jun 4, 2021
Priority date	Apr 23, 2018
Publication date	Nov 8, 2022
Grant date	Nov 8, 2022

Abstract

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

First claim

What is claimed is:

1. A method of operating a memory device including a non-volatile memory array, comprising:
sending a command to the memory device to configure a subset of the non-volatile memory array to erase or degrade data stored therein in response to a changed power condition of the memory device; and
storing data in the subset of the non-volatile memory array configured to be erased or degraded in response to the changed power condition of the memory device.

2. The method of claim 1 , wherein the subset comprises one or more addresses, and wherein the command instructs the memory device to store the one or more addresses in a write-once read-many (WORM) memory of the memory device.

3. The method of claim 2 , wherein the write-once read-many (WORM) memory comprises an array of fuses, anti-fuses, or a combination thereof.

4. The method of claim 1 , wherein the subset comprises one or more addresses, and wherein the command instructs the memory device to store the one or more addresses in a register of the memory device.

5. The method of claim 1 , wherein the non-volatile memory array comprises NAND flash, NOR flash, MRAM, FeRAM, PCM, or a combination thereof.

6. The method of claim 1 , further comprising effecting the changed power condition to trigger erasure or degradation of the stored data.

7. The method of claim 1 , wherein the data is first data and the subset is a first subset, further comprising storing second data in a second subset of the non-volatile memory array configured to retain the data through the changed power condition of the memory device.

8. The method of claim 1 , wherein the subset comprises a first address range, and wherein the command instructs the memory to store a second address range exclusive of the first address range.

9. The method of claim 1 , wherein the subset is configured to erase or degrade the data in response to the changed power condition of the memory device by overwriting the data with a pseudorandom pattern.

10. The method of claim 1 , wherein sending the command is performed by an end user of the memory device.

11. The method of claim 1 , wherein sending the command is performed during the manufacture of the memory device.

12. The memory system of claim 1 , wherein the data is configured to be erased or degraded subset is configured to erase or degrade the data in response to the changed power condition of the memory device by overwriting the data with a pseudorandom pattern.

13. A memory system, comprising:
a memory device including a non-volatile memory array; and
a memory controller configured to:
send a command to the memory device to configure a subset of the non-volatile memory array to erase or degrade data stored therein in response to a changed power condition of the memory device, and
store data in the subset of the non-volatile memory configured to be erased or degraded in response to the changed power condition of the memory device.

14. The memory system of claim 13 , wherein the subset comprises one or more addresses, and wherein the command instructs the memory device to store the one or more addresses in a write-once read-many (WORM) memory of the memory device.

15. The memory system of claim 14 , wherein the write-once read-many (WORM) memory comprises an array of fuses, anti-fuses, or a combination thereof.

16. The memory system of claim 13 , wherein the subset comprises one or more addresses, and wherein the command instructs the memory device to store the one or more addresses in a register of the memory device.

17. The memory system of claim 13 , wherein the non-volatile memory array comprises NAND flash, NOR flash, MRAM, FeRAM, PCM, or a combination thereof.

18. The memory system of claim 13 , wherein the data is first data and the subset is a first subset, and wherein the memory controller is further configured to store second data in a second subset of the non-volatile memory array configured to retain the data through the changed power condition of the memory device.

19. The memory system of claim 13 , wherein the subset comprises a first address range, and wherein the command instructs the memory to store a second address range exclusive of the first address range.

Assignees

• Micron Technology Inc

Inventors

• Cowles Timothy B
• Raad George B
• Rehmeyer James S
• Parry Jonathan S

Classifications

• G11C7/24 Primary

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title

• G11C11/2295

  Protection circuits or methods · CPC title

• G11C11/1695

  Protection circuits or methods · CPC title

• G11C11/1697

  Power supply circuits · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title