3D NAND memory device and method of forming the same

Patent metadata

Field	Value
Publication number	US-11737263-B2
Application number	US-202117446006-A
Country	US
Kind code	B2
Filing date	Aug 26, 2021
Priority date	Sep 13, 2018
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

In a three-dimensional memory device, an interconnect structure is formed over a substrate and a first deck is formed over the interconnect structure. The first deck includes alternating first insulating layers and first word line layers, and a first channel structure extending through the first stack. The first channel structure has a first channel dielectric region and a first channel layer. The first channel dielectric region is formed along sidewalls of the first channel structure, positioned over a top surface of the interconnect structure, and in contact with the first insulating layers and the first word line layers. The first channel layer is formed along the first channel dielectric region, and includes a rounded projection that extends away from the top surface of the interconnect structure, extends outwards into the first stack at an interface of the interconnect structure, the first channel structure and the first stack.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
an interconnect structure; and
a first deck formed over the interconnect structure, the first deck including a
first stack of alternating first insulating layers and first word line layers over the interconnect structure, and a first channel structure extending through the first stack, the first channel structure having sidewalls and a bottom portion that vertically extends into a recess of the interconnect structure, the first channel structure having a first channel dielectric region and a first channel layer including side portions and a bottom portion, wherein:
the first channel dielectric region is formed along the sidewalls of the first channel structure, positioned over a top surface of the interconnect structure, and in contact with the first insulating layers and the first word line layers,
the side portions of the first channel layer are formed along the first channel dielectric region, and include a rounded projection that extends away from the top surface of the interconnect structure, extends outwards into the first stack to form a curved interface with the first stack at an interface of the interconnect structure, the first channel structure and the first stack, and is positioned between the first channel dielectric region and the bottom portion of the first channel layer, and
the bottom portion of the first channel layer is formed along the recess of the interconnect structure and in contact with the interconnect structure.

2. The three-dimensional memory device of claim 1 , wherein:
the first channel dielectric region is positioned on the rounded projection of the side portions of the first channel layer.

3. The three-dimensional memory device of claim 1 , wherein:
the side portions of the first channel layer further comprises a tapered structure that is formed along the first channel dielectric region, and
the rounded projection is positioned between the tapered structure and the bottom portion of the first channel layer.

4. The three-dimensional memory device of claim 3 , wherein:
a top of the rounded projection is positioned above a bottom of the tapered structure.

5. The three-dimensional memory device of claim 2 , wherein the first channel dielectric region comprises:
a first blocking layer formed along the sidewalls of the first channel structure, the first blocking layer being in contact with the first insulating layers and the first word line layers and positioned on the rounded projection of the side portions of the first channel layer,
a first charge storage layer formed along the first blocking layer and positioned on the rounded projection of the side portions of the first channel layer, and
a first tunneling layer formed along the first charge storage layer and positioned on the rounded projection of the side portions of the first channel layer.

6. The three-dimensional memory device of claim 1 , wherein the rounded projection extends outwards into a lowermost insulating layer of the first insulating layers in the first stack.

7. The three-dimensional memory device of claim 1 , wherein the first channel structure further comprises:
a first dielectric layer formed over the first channel layer in the first channel structure, and extending into the interconnect structure; and
a first channel contact formed along the first channel layer and positioned over the first dielectric layer.

8. The three-dimensional memory device of claim 1 , further comprising:
a substrate; and
a second deck positioned between the substrate and the interconnect structure, the second deck including a second stack of alternating second insulating layers and second word line layers over the substrate, and a second channel structure extending through the second stack, the second channel structure having sidewalls and a bottom portion that vertically extends into the substrate.

9. The three-dimensional memory device of claim 8 , wherein the second channel structure further comprises:
a second channel contact positioned at the bottom portion of the second channel structure and extending into the substrate;
a second blocking layer formed along the sidewalls of the second channel structure and arranged between the second channel contact and the interconnect structure, the second blocking layer being in contact with the second insulating layers and the second word line layers;
a second charge storage layer formed along the second blocking layer and arranged between the second channel contact and the interconnect structure;
a second tunneling layer formed along the second charge storage layer and arranged between the second channel contact and the interconnect structure;
a second channel layer formed along the second tunneling layer and arranged between the second channel contact and the interconnect structure, the second channel layer being connected with the interconnect structure; and
a second dielectric layer formed along the second channel layer and arranged between the second channel contact and the interconnect structure.

10. The three-dimensional memory device of claim 9 , wherein the first channel structure and the second channel structure have a pillar-shape.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Ruo Fang
• Wang Enbo
• Yang Haohao
• Xu Qianbing
• Hu Yushi
• Zhang Fushan

Classifications

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title