Low powered clock driving

Patent metadata

Field	Value
Publication number	US-11736095-B2
Application number	US-202217987189-A
Country	US
Kind code	B2
Filing date	Nov 15, 2022
Priority date	Jun 15, 2021
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.

First claim

What is claimed is:

1. A system comprising:
a plurality of signal processing blocks, wherein each of the plurality of signal processing blocks are stacked and share a same current, wherein one or more intermediate signal processing blocks of the plurality of signal processing blocks comprises a broadband signal processing block;
a distribution network receiving, as input, an output of the plurality of signal processing blocks; and
a plurality of array elements each receiving an input from the distribution network.

2. The system of claim 1 , wherein the plurality of signal processing blocks comprises an oscillator, a multiple phase divider, and a buffer.

3. The system of claim 1 , wherein the plurality of signal processing blocks comprises a first amplifier, a delay network, and a second amplifier, and wherein the plurality of array elements comprise a plurality of third amplifiers in a beamformer.

4. The system of claim 1 , wherein the plurality of signal processing blocks comprises a single ended oscillator, a single ended divider, and a differential buffer.

5. The system of claim 1 , wherein the distribution network is stacked with the plurality of signal processing blocks.

6. The system of claim 1 , wherein the plurality of array elements includes one of an array of antennas, an array of memory modules, an array of sensors, and an array of quantum computing channels.

7. The system of claim 1 , wherein the output of the plurality of signal processing blocks is a divided clock signal.

8. An apparatus comprising:
a plurality of signal processing blocks, wherein each of the plurality of signal processing blocks are stacked and share a same current, wherein one or more intermediate signal processing blocks of the plurality of signal processing blocks comprises a broadband signal processing block; and
a distribution network receiving, as input, an output of the plurality of signal processing blocks.

9. The apparatus of claim 8 , wherein the plurality of signal processing blocks comprises an oscillator, a multiple phase divider, and a buffer.

10. The apparatus of claim 8 , wherein the plurality of signal processing blocks comprises a first amplifier, a delay network, and a second amplifier.

11. The apparatus of claim 8 , wherein the plurality of signal processing blocks comprises a single ended oscillator, a single ended divider, and a differential buffer.

12. The apparatus of claim 8 , wherein the output is a divided clock signal.

13. The apparatus of claim 8 , wherein a distribution network is stacked with the plurality of signal processing blocks.

14. A method comprising:
generating, by a circuit comprising a plurality of signal processing blocks, an output signal, wherein each of the plurality of signal processing blocks are stacked and share a same current, wherein one or more intermediate signal processing blocks of the plurality of signal processing blocks comprises a broadband signal processing block; and
providing, by the circuit, the output signal to a distribution network.

15. The method of claim 14 , wherein the plurality of signal processing blocks comprises an oscillator, a multiple phase divider, and a buffer.

16. The method of claim 14 , wherein the plurality of signal processing blocks comprises a first amplifier, a delay network, and a second amplifier.

17. The method of claim 14 , wherein the plurality of signal processing blocks comprises a single ended oscillator, a single ended divider, and a differential buffer.

18. The method of claim 14 , wherein a distribution network stacked with the plurality of signal processing blocks.

19. The method of claim 14 further comprising:
receiving, by a plurality of array elements, an input from the distribution network.

20. The method of claim 19 , wherein the plurality of array elements includes one of an array of antennas, an array of memory modules, an array of sensors, and an array of quantum computing channels.

Assignees

• IBM

Inventors

• Ramirez Daniel
• Chakraborty Sudipto

Classifications

• H03K3/353 Primary

  by the use, as active elements, of field-effect transistors with internal or external positive feedback (H03K3/023, H03K3/027 take precedence) · CPC title

• H03K5/13 Primary

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• H03K2005/00195

  using FET's · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title